Hello,
I am using the Intel I2C Master IP Core to communicate with a temperature sensor (TMP75B) on a custom PCB including an Arria 10 GX FPGA. The hardware is not yet present therefore I am currently simulating the components with ModelSim.
The Qsys subsystem under test includes the I2C Master IP Core, my custom VHDL component that interacts with it and the Intel I2C Slave IP Core together with a On-Chip RAM for test purposes. In hardware the I2C Slave and the RAM will be replaced by the temperature sensor.
The subsystem also includes a I2C bridge, that connects the SDA and SCL pins via pull-up logic.
entity temp_tb_i2c_bridge is
port (
sda_in_master : out std_logic; -- i2c_master.sda_in
scl_in_master : out std_logic; -- .scl_in
sda_oe_master : in std_logic := '0'; -- .sda_oe
scl_oe_master : in std_logic := '0'; -- .scl_oe
data_in_slave : out std_logic; -- i2c_slave.conduit_data_in
clk_in_slave : out std_logic; -- .conduit_clk_in
data_oe_slave : in std_logic := '0'; -- .conduit_data_oe
clk_oe_slave : in std_logic := '0' -- .conduit_clk_oe
);
end entity temp_tb_i2c_bridge;
architecture a_temp_tb_i2c_bridge of temp_tb_i2c_bridge is
begin
sda_in_master <= '0' when data_oe_slave = '1' else
'0' when sda_oe_master = '1' else 'H';
scl_in_master <= '0' when scl_oe_master = '1' else
'0' when clk_oe_slave = '1' else 'H';
data_in_slave <= '0' when sda_oe_master = '1' else
'0' when data_oe_slave = '1' else 'H';
clk_in_slave <= '0' when scl_oe_master = '1' else
'0' when clk_oe_slave = '1' else 'H';
end architecture a_temp_tb_i2c_bridge;The temp_ctrl component first initializes the I2C Master (SCL, SDA timing) and then waits for Avalon-MM read/write commands.
The write command works out fine: The temp_ctrl components fills the I2C Master up with commands for e.g. writing 2 Byte containing 0x1234.
The values written to the I2C master TFR_CMD register are:
0x20A (Start+Address=5+Write),
0x000 (Register=0),
0x034 (write first data byte),
0x112 (Stop+write second data byte).
I can see the I2C Slave writing the value 0x1234 to the RAM address 0 after that.
When reading from the same RAM address, I am using the following commands:
0x20A (Start+Address=5,Write),
0x100 (Stop+Register=0),
0x20B (Start+Address=5+Read),
0x000 (read first data byte),
0x100 (stop + read second data byte).
This works out fine too until the I2C master has to send the ACK after receiving the first data byte - it just doesn't do it.
As you can see in the image above, the master does send the Start+Address=5+Write (red), the Stop+Register=0 (purple) and then the Start+Address=5+Read (green). The master then receives the first data byte (0x34) from the slave (orange).
But after receiving the first data byte the I2C master doesn't generate a 9th clock with an ACK and the transmission of the second data byte is not started.
Does anybody know why the I2C Master behaves this way or what I am doing wrong?
Best Regards
Florian
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