IP Example Design (DDR4 IP) Synth only Missing Libraries?

[Paul44]

Hi, please could I ask a question.

Using Quartus prime pro (v24.1) to generate a basic DDR4 IP design targeting an Agilex7 device.

Early stages of design. Just wishing to instantiate ddr4 ip block to perform a DRC (Design Rules Check) and confirm pin allocation etc.

I have created a new top level design. Run platform designer to generate a ddr4 ip block and used the 'example design' to generate a suite of synthesis only files. When I run the compilation it fails because the generated files require an 'altera_interconnect_1920' library to be setup. I can see a verilog file for the missing library but how do I create or compile a library from it? The generated ip block does use additional libraries but these seem to be covered  by a .qsys and various *.ip files. Do I need to generate a .ip file for the missing 'altera_interconnect_1920' ?

Thanks in advance for any guidance:) P

[sstrell]

Generating an example design should create all the files you need.  So you generate the example design which creates an ed_synth directory, you open the .qpf in there (the new example design project) and try to compile and you're getting this error?

That is very odd.

I'd trash the ed_synth directory and try to generate it again.  That should not happen.  The whole point of the example design is that it is a complete project that you generate and then compile.

Edit: or are you saying you did not switch to the new example design project but still trying to compile?  Yeah, that won't work.  You have to open the new generated project and then compile.

[HubertG]

Hi Paul44, I have received your question ^^ Can I request some time from you to let me check and confirm with the team and get back to you soon ?

-Always at your service-

Thanks

Hubert

[HubertG]

Hi Paul44, can I request some of the information from you below in order for us to have a better understanding and to support you ?

1. Is your generated standalone design working ?
2. May I know the purpose of creating a new top level design rather using the example design ?
3. So far, can I know that which of the steps that you have been taken which prompt you the error message ? What error message it written ?

Thanks

Hubert

[HubertG]

Hi Paul44, can I request some of the details of the info from you which written in the earlier message ?

Thanks

Hubert

[HubertG]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.