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We have a board design with an Arria 10 and a single Micron LPDDR3 IC. Mostly it works. But on occasion, the device comes out of reset with the EMIF PLLs locked, but neither cal_success nor cal_fail indicated. The EMIF is not functional at this time.
This may happen after a board reset from a working condition.
Under software control, the EMIF global_reset_n line can be puled low, but this does not fix the issue. A board reset of the Arria also does NOT fix the problem once this mood is entered, only a power-cycle of the board does.
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Hi KCMurphy,
Is the EMIF IP has been setup with correct parameter by referring to memory datasheet and board simulation?
Is the design has fully constrained?
Are you able to see similar behavior with other board if applicable?
Regards,
Adzim
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We believe this was a power sequencing issue. If we hold the EMIF interface in reset until our controller releases it, the calibration proceeds correctly.
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Hi KCMurphy,
The emif user reset should be released after the calibration is finished to avoid interruption during the calibration process.
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