MAX 10-Triple speed Ethernet IP Megacore

[Altera_Forum]

Hello everyone. Can anyone please let me know if MAX 10 is supported by Triple speed Ethernet megacore function or not? I was trying to find out from the documentation but could not find anything. Thank you

[Altera_Forum]

https://cloud.altera.com/devstore/platform/15.1.0/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/

[Altera_Forum]

Thank you very much

[Altera_Forum]

"Error (204012): Can't generate netlist output files because the file "E:/Quartus/test/ethernet/altera_eth_tse_mac.v" is an OpenCore Plus time-limited file. Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 

 Hi again...i was trying to compile TSE megacore function but it is showing this error message. Is it because of license issue? I thought it doesnt require license. Am i doing anything wrong? Thanks in advance for help.

[Altera_Forum]

The error is telling you that you need a license to generate a simulation netlist. 

You can ignore that error if you don't want to generate a netlist.

[Altera_Forum]

Thanky you for your answer. Actually i am trying to send 16 bit data through FPGA to PC. For that i am using a shift register and FIFO before data proceed to ethernet megacore function. There are some files generated from the ethernet megacore function including a instantiate file. If i instantiate my shift register and fifo module inside the ethernet instantiation file is that okay or am i doing anything wrong? Appreciate your kind advice. Thanks