Memory Interface : Arria_10 NIOS II + Address span extender + EMIF (x72 arria 10 GX DDR4 HILO)

[Jacky_chang]

NIOS II has a limit of 32bit data length, I need to turn on Cache and use EMIF, the bridge is Address span extender,

How to define IP parameters for the address span extender between NIOS II and EMIF(x72 arri10gx DDR4 HILO).

Could you provide project (.par) reference?

thank you very much.

FPGA board : Intel® Arria® 10 GX FPGA Development Kit

FPGA chip part number : 10AX066H2F34I2SG

Quartus Prime Pro 23.3

[JingyangTeh]

Hi

Could not find any example design that you are looking at.

However I managed to gather some related document on configuring the Address Span extender in the link below:

https://community.intel.com/t5/FPGA-Wiki/Address-span-extender-example/ta-p/735149

https://www.intel.com/content/www/us/en/docs/programmable/683609/24-2/address-span-extender.html

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh