I've been modifying my project from 40G ethernet to use the Intel 10G LL MAC. I removed the old MAC, and inserted the generated project for the 10G LL MAC into the design but when I connect a fiber from my project to a separate tower, no link status lights are visible on the tower.
I've double checked all the clock requirements and have been working through the CSR documentation and the Debug Checklist on this forum. The CSR states that tx and rx are both enabled and not stuck in reset. I didn't see any other registers in the CSR document that had relevant information. I've never messed with the CSR configuration with the 40G so I'm assuming the config defaults should be fine. All IP have been updated. I have no timing failures. All resets appear to be working correctly. The design works fine with 40G and the only changes have been instantiating the generated 'altera_eth_top' module into my design.
I'm relatively new to these kinds of protocols and not sure where to go next. The initial plan was to compile the 10G example design on its own without integrating it to confirm it works but I need an HPS to run necessary scripts before I can confirm it works. So I decided to go to integration rather than getting an HPS inserted into the example design.
Any help in figuring out how to debug this is greatly appreciated!
