PCIe HIP - only one legacy INTX interrupt available

[jmcguire3]

I have a legacy support task - obsolete hardware, critical system, etc - where I need to emulate some old, obsolete, unobtanium peripheral components in an FPGA.  The peripherals in the system use the INTx legacy interrupts.  I can successfully instantiate each of two emulated PCI peripheral devices, and they work properly in isolation.  However, for the life of me, I can't seem to get the Platform Designer tool to let me have access to more than one INTx interrupt.  Maybe I'm thick, but the PCIe HIP documentation rather explicitly states that intx_req_i should be a vector [3:0].  However, in the Platform Designer tool, I cannot change the width parameter - it's stuck (grey) with a value of "1".  I can change the pull-down type below the width parameter from "standard logic" to "standard logic vector," but that doesn't allow me to edit the width parameter.

I tried or-ing my legacy interrupts together externally, and they were properly detected in the system and assigned the same legacy interrupt ... which prompty crashed the host PC.  I have tried to widen the INTx parameter in Quartus 19.4, 21.1, and most recently in 22.1.  Not sure what I'm missing.

[Kenny_Tan]

Hi,

Thanks for using Intel community forum,

Kindly expect some delay in the reply due to holiday.

Thanks,

[wchiah]

Hi,

Thanks for reaching, May I know which device and user guide you are referring?

PCIe endpoint supports both legacy interrupts and MSI interrupts.

However, MSI and legacy interrupts are mutually exclusive, it means only 1 type of interrupt can be enabled at a time.

To switch interrupt mode during operation, software must first enable the new mode and then disable the previous mode.

To enable legacy interrupts when the current interrupt mode is MSI, software must first turn off the Disable Interrupt

bit (bit[10] of the Command register at configuration space offset 0x4) and then turn off the MSI Enable bit.

1. Off the Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to enable legacy interrupt.

2. Off the MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.

3. Set the bit[1] Memory Space and Bus Master bit[2] of Command Register at configuration space offset register 0x4 to enable the ability to generate/send MSI message.

Once app_int_sts is asserted by its source, the PCIe core will sends out an Assert_INTA message TLP to root port.

Below link also has information about legacy interrupt, help it helps.

https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044

Regards

Wincent_Intel

[jmcguire3]

This is a legacy interrupt availability issue ... has nothing to do with MSI.  In fact, I have no resources available to configure MSI registers on the target platform, and the legacy interrupt operates properly with a single device attached.

Problem exists for both a Cyclone 10 GX and Stratix 10 MX target device - the latter having an H-tile PCIe HardIP core, whereas the former has the HardIP integrated onto the FPGA die.  The Cyclone documentation suggests support for multiple INTx interrupts, but the H-tile document comes right out and says so -

3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an... (intel.com)

However, I am unable to configure the Hard IP through Platform Designer to allow access to more than one legacy INTx interrupt.  When the pull-down menu is changed to "standard logic vector," the width field remains gray and is fixed to "1".  (screenshot is attached)

[wchiah]

Hi,

Do you clear the Interrupt Disable bit, which is bit 10 of the Command register?
Also, please ensure that you had turned off the MSI Enable bit.

Let me know if the problem still happen after that.

Regards,

Wincent_Intel

[jmcguire3]

Apparently I wasn't clear - allow me to clarify.  This isn't a run-time configuration issue, it's a compile-time resource allocation.  The CRA is not enabled in the Platform Designer tool (see attached.) The "CRA Avalon-MM slave port" box is un-checked, so there is no interface with which to set or clear bits in the PCIe IP register set.  The "Export MSI/MSI-X interfaces" box is checked, as this is necessary to expose the INTx legacy interrupt conduit to the Platform Designer interconnect area.  

Only one INTx interrupt shows up.  In isolation it works fine.  I need to add another legacy peripheral that expects to use the hardware-driven INTA/INTB/INTC/INTD legacy interrupts held over from the olden PCI days - from back when PCI cards had access to only the four INTx hardware interrupts and MSI hadn't been invented yet.  The Platform Designer tool refuses to allow me to change the width of the INTx interface to anything other than "1".  The documentation referenced upthread indicates that it can have a width of 4, corresponding to the legacy PCI INTA/B/C/D structure.

[wchiah]

Hi,

Apologize that I am out of office few days due to Sick.

Will get back to you with your question soon as possible.

Again, I do apologize for any inconvenience caused.

Regards

Wincent_C

[wchiah]

Hi,

Apologize for late reply, I am able to replicate your issue using Stratix 10 AVMM design example.

Then intx_req_i signal indeed only "1" is available.

I might need more time to investigate this issue. Get back to you soon as possible.

Regards,

Wincent_C

[wchiah · Accepted solution]

Hi,

Apologize for late, hope this helpful.
There is two AVMM example available in the Quartus, one is AVMM another one is AVMM+

• For the AVMM example design indeed you will get "1"

The document provided by you early 3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an... (intel.com)

Shows that the 4bits intx_req_i is only available for AVMM+

I try to run the example design (AVMM+) and I get the result below

Let me know if this is helpful, please correct me if i am wrong.

Regards,

Wincent_C

[wchiah]

Hi,

I strongly believe my previous reply answered your question. 

We do not receive any response from you to the previous answer that I provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel