PCIe traffic from fpga

[Altera_Forum]

Hello, 

   I am having some problems in sending data from FPGA to a processor via PCI express by using dev kits.   I manage to send data from processor to FPGA via PCI express, but not vice versa.   I write to the PCIexpress IP instantiated in Qsys in the dedicated Tx slave Avalon memory mapped port and the avalon write seems correct, but I do not manage to find the written data on the processor memory.   The SW in the processor should be ok, but we are not 100 % sure (we are investigating also there).   Do you have any suggestion to help us in the debug, in verifying that the data is actually going out of the fpga?   For example could I sample in signaltap the data I am sending in the tx_out0 line ?   If so, which clock should I use in signaltap in order to sample it?  What is precisely the expected behaviour of tx_out0 ?   Thanks

[Altera_Forum]

Have you enabled Bus Mastering? There is a bit in the configuration space that determines whether or not the device should be allowed to send data autonomously on the PCIe bus (a process called bus mastering). This is usually something the OS will enable if your driver asks for it. How to enable it will depend on what OS you use (Linux vs. Windows) and what driver framework you build on.