Problem W/ Altera VIP Frame Buffer II

[EvanHamiltonJAVS]

I have configured an FPGA design for my linux device that is displaying SDI and HMDI inputs. It was originally configured to receive YCbCr 4:2:2 video format. Since I am experiencing green spill on images when trying to chroma key, I am attempting to change the input data to RGBA. 

For a test, I have implemented a conversion into the FPGA that handles the RGB input from the frame buffer. I believe this conversion is correct because the color values come out as expected.

FPGA Design Here:

FB -> CSC -> CRS -> Output

This is the same for all four mixers.

I am using gstreamer to input the color bars pattern into the pipeline.

(gst-launch-1.0 videotestsrc ! videoconvert ! video/x-raw,format=BGR,width=1920,height=1080 ! videoconvert ! filesink location="/dev/fb3")

There are 4 frame buffers located at "/dev/fb0", "/dev/fb1", and so on.

Basically the issue is these frame buffer's graphics are overlapping and changing the memory regions in the DTS file does not fix the issue:

"gst-launch-1.0 videotestsrc ! videoconvert ! video/x-raw,format=BGR,width=1920,height=1080 ! videoconvert ! filesink location="/dev/fb0"

"gst-launch-1.0 videotestsrc ! videoconvert ! video/x-raw,format=BGR,width=1920,height=1080 ! videoconvert ! filesink location="/dev/fb1"

"gst-launch-1.0 videotestsrc ! videoconvert ! video/x-raw,format=BGR,width=1920,height=1080 ! videoconvert ! filesink location="/dev/fb3"

I can even see the bottom portion of the color bars pattern when changing the height to 720.

"gst-launch-1.0 videotestsrc ! videoconvert ! video/x-raw,format=BGR,width=1920,height=720 ! videoconvert ! filesink location="/dev/fb3"

The drivers being used for the frame buffer is altvipfb.c and altvipfb2-plat.c

Here is the DTS snippet of these frame buffer components and the boot logs where the frame buffers are initialized:

DTS snippetBoot Logs

The virtual address and length seen in these boot logs do not change at all when DTS changes are made.

I also get this error when inputting a pipeline:

If anyone could help me approach this issue it would be greatly appreciated.

Thanks,

Evan

[ZH_Intel]

Hi Evan,

Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel