Stratix 10 Calibration Native Phy and Atx Pll

[Petkov_Alex]

Hello. I have read document xcvr h/l tile stratix 10, and tested my project in ModelSim
I have 4 channels native phy with multiple profiles saved and embedded reconfiguration streamer
2 Atx pll with multiple profiles and embedded reconfiguration streamer
Timing for reconfiguration and calibration in simulation takes 3000-4000 clocks at 125 MHz.
But in hardware it takes 20-25 000 000 clocks at 125 MHz, the most time it take in atx pll calibration and tx/rx native phy calibration...
Can I not to use calibration in hardware, or what timing required for calibration. User_clk_1 have stable and free running clock from external oscillator.

[Petkov_Alex]

Without calibration atx pll not locks at all

[Kshitij_Intel]

Hi,

Please share the OPN.

Have you selected the correct configuration clock source(i.e. 125 MHz OSC_CLK_1 pin) in Device and Pin options?

Please refer the Calibration chapter in L- and H-Tile Transceiver PHY User Guide.

Also, the time required to complete the calibration process after device power-up can vary by device.

Thank you

Kshitij Goel

[Petkov_Alex]

No, you did not understand, my OSC_USER_CLK1 is stable and free running, and has 100MHz clk, and it selected in project settings.
My Reconfig_clk has 125 MHz and takes Several Millions of clock beginning from start of reconfiguration and recalibration to pll locked and calibrated. But if I do not recalibrate, pll not locks at all

[Kshitij_Intel]

Hi,

If you are using E-Tile device, It is mandatory to do the initial adaptation. Also, It is expected there would be significant differences in calibration time between simulation and hardware.

Thank you

Kshitij Goel

[Petkov_Alex]

Ok, thanks. Can you explain or describe, what affects on calibration time in hardware?

[Kshitij_Intel]

Hi Alex,

We should think about what calibration is actually doing. Essentially, we are tuning out “physical” silicon tolerance errors caused by manufacturing process variation, and selecting the correct VCO for the given data rate and REFCLK. Calibration is very much an analogue process that happens on the silicon device that can take milliseconds in some cases.

In contrast, when you simulate the calibration process, there is no silicon for this process to act upon. So I expect that we just mimic the calibration process taking place so that you can see it taking place. It would be incredibly time consuming if you had to simulate a transceiver for milliseconds before they could see the outcome of the dynamic reconfiguration and calibration process. For that reason, calibration in a simulation environment is kept conveniently short so users can focus on the important things like “is the transceiver is working properly after dynamic reconfiguration and calibration”.

Are you failing to meet a protocol spec?

Thank you

Kshitij Goel

[Petkov_Alex]

Thanks for explaining.
Yes, I failing to meet protocol specs.
I thought about another scheme to use TX PLLs and decided to use
One fpll in Transceiver mode with MCGB, with multiple profiles.
One ATX pll with also MCGB for higher speed, without reconfiguration. Mcgb because of need for 4 channels.
So fpll recalibration time meets time requirements.
And Native Phy with 2 tx pll inputs.
I read xcvr user guide and have some questions about 6.15 "unsupported features", can you explain about Reconfiguration MCGB and switching between two MCGB

[Petkov_Alex]

[Petkov_Alex]

And one more question, in documentation, fpll max supported speed in Transceiver mode is 12,5 gbps, but when i tried to set higher speed, for example 7000 GHz Platform Designer dod not give me error. So my question is, it is not error, but it would not work?

[Kshitij_Intel]

Hi,

Can you please share which protocol specs you are failing to meet?

Can you please explain what explanation you are looking for these unsupported features i.e. Reconfiguration MCGB and switching between two MCGB? 

Also, Depending on your target data rate you have to choose the type of PLL.

Thank you

Kshitij Goel

[Petkov_Alex]

Infiniband
Can i use fpll as MCGB and dynamic reconfiguration it with profiles?
Can I use fpll with mcgb and dynamic reconfiguration and atx pll with mcgb without dynamic reconfiguration. They goes to native phy serial clk 0 and 1. And I can mux them in native phy via reconfiguration interface.
Can i use fpll in Transceiver mode for 7GHz?

[Kshitij_Intel · Accepted solution]

Hi,

Q1. Can I use fpll as MCGB and dynamic reconfiguration it with profiles?

Ans - Yes.

Q2. Can I use fpll with mcgb and dynamic reconfiguration and atx pll with mcgb without dynamic reconfiguration. They goes to native phy serial clk 0 and 1. And I can mux them in native phy via reconfiguration interface.

Ans - It should be, please looked into the IP, If there are profiles in the dynamic reconfiguration tab, then profiles are supported.

Q3. Can i use fpll in Transceiver mode for 7GHz?

Ans - Maximum frequency for fPLL is 12.5Gbps (6250MHz).

Thank you

Kshitij Goel

[Petkov_Alex]

Thanks for your answer!

[Kshitij_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel