Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

[BKB]

Hi,

We have two DDR4 EMIFs on each die of 1SG10MHN3F74C2LG_U1 FPGA on our boards. The earlier implementation of our board had mistakes and the control address pins were split across banks and also part of two EMIfs address/control were on one bank which led to size limitations. I have attached the pages of schematic showing the original pinout.

I remapped the pins such the address/control pins are in the same bank and also the two EMIFs address/control IO don't share a bank. I have attached the project archive of the example design with two EMIF. I have also uploaded qsf file and the fit report. The example design implements without errors but if I use the same pin map for EMIF along with other IOs on the board, the implementation fails. i have uploaded the complete pin list and the fit report of our implementation. The errors are on the pin are the same as from the original pinout. Please help fix the error. Please let me know if I can provide any further information. 

Best,

BB

[AdzimZM_Intel]

Hi BB,

What is the difference between ddr_u1 and ed_synth?

Is it on different design and device?

How many EMIF IP in your design?

The Quartus version is 22.3, correct?

Regards,

Adzim

[AdzimZM_Intel]

Hi @BKB 

May I know if this issue still occurs at your end?

Regards,

Adzim

[BKB]

Hi Adzim,

Sorry, I completely missed your earlier response. I was able to resolve the error.

ed_synth is the example design generated by quartus. I modified it to have two instances of EMIF to replicate what we have in our design. ddr_u1 is our internal design with all other interfaces, clocks and internal logic. It has two EMIF instances.

As I had explained, whoever designed the board earlier did a mistake and some I/Os of both EMIF were on a common I/O bank which rendered those IOs unusable and we were limited to access a smaller size of DDR4. When I split the IOs using the common bank, across two banks, the extra I/O bank used also had reference clock coming in. So quartus fit flagged an error. But the error messages were not helpful as the fit errors were in a bank complete EMIF IO. and not in the bank where the  reference clock was coming in. I copared that bank with the other banks and the other instance which implemented fine and experimented with moving the reference clock to other bank and it worked.

The tool does need to give more readable/understandable errors for EMIF implementatioon.

Best,

BB

[sstrell]

I'd bring the design into Interface Planner to verify the legal locations for the adjustments you are making to pin placement.

[BKB]

Thank you. I was able to implement our design with the revised pin map once I move the reference clocks to a different bank. 

Best,

Bharat