Stratix 10 H-Tile Avalon Streaming PCIe IP Core - Root Port Configuration Space access

[tm1701]

Hello,

I'm using the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express configured as Root-Port on a Stratix 10 MX FPGA.

My question is, how do I access the Root-Ports configuration space from my application logic?

I couldn't find any information how to do so in User Guide of the Stratix-10 Avalon Streaming PCIe IP Core.

The User-Guide for the Arria10 and Cyclone 10 GX Avalon Streaming IP-Core, on the other hand, has a chapter (chapter 10.2) that tells to access Root-Ports configuration space by issuing Configuration Requests of Type-0 on the AVST TX Interface.

Quote:

• In Root Port mode, the Application Layer can issue Type 0 or Type 1 Configuration TLPs on the Avalon-ST TX bus.
• The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are not sent downstream on the PCI Express link.

As I couldn't find any such information in the User Guide of the Stratix-10 IP Core I tried to do the same with my Stratix-10 design. However, configuration request of Type-0 are forwarded downstream to the Endpoint on the other side of the PCIe-Link.

Any help is appreciated!

Kind regards.

[Wincent_Altera]

Hi,

If I check the KDB below

https://www.intel.com/content/www/us/en/support/programmable/articles/000080857.html

Type 0 Root Port Mode Configuration Requests capability for Stratix 10 is not supported.

Let me know in case I missunderstand your question. Hope that answered your question.

Regards,

Wincent_Intel

[tm1701]

Hello,

---

@Wincent_Altera wrote:

Hi,

If I check the KDB below

https://www.intel.com/content/www/us/en/support/programmable/articles/000080857.html

Type 0 Root Port Mode Configuration Requests capability for Stratix 10 is not supported.

Let me know in case I missunderstand your question. Hope that answered your question.

Regards,

Wincent_Intel

---

thank you for the swift response, this answers my question.

However I have a follow up question:

The aforementioned Arria10 and Cyclone 10 GX Avalon Streaming IP-Core User Guide further mentions rules regarding the routing of TLPs in Chapter 10.2.

Specifically it notes:

"The Transaction Layer sends all memory and I/O requests, as well as completions generated by the Application Layer and passed to the transmit interface, to the PCI Express link."

Does this statement hold true for the Stratix-10 HIP core aswell?

If I get this statement right, it effectively means the base and limit registers in the Root-Ports Type-1 configuration space header are ignored.

Thank you and kind regards!

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

Arria 10, Cyclone 10 have some different compare with Stratix 10.

I dont think you can direct relate between both of them.

Detail, you better refer back to 

• 6.1.14. Transaction Layer Configuration Space Interface

Regards,

Wincent_Intel

[tm1701]

Thank you once again for your response!

The reason I refer to the Arria10, Cyclone 10 User Guide, is because I cannot find any Information regarding TLP-Routing in the Stratix 10 User Guide.

However, I think that information is also necessary on the Stratix 10 to properly use the PCIe IP-Core. My experience from Simulation suggests, that the Stratix 10 Root-Port IP-Core does indeed forward all Memory-Request to the PCIe-Link, ignoring Memory Base and Limit Registers in the Root-Ports Configuration Space Header.
It would be reassuring to know, whether that's the intended way to use the IP-Core.

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

The best thing I can do is file an internal ticket to the document team to request emphasis on the importance of having TLP Routing information in Stratix 10 document.

Hope they will add that in the coming release document.

Meanwhile, is there anything else I can help/clarify?

Regards,

Wincent_Intel

[tm1701]

Hello,

no, from my end the forum ticket could be closed.

Thank you for your help!

Kind regards!

[Wincent_Altera]

Hi

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Regards,

Wincent_Intel