Warnings when fitter max10 + NIOS + UNIPHY

[XQSHEN]

Below warning are generated when fitter 10M16DCU324I7G

Nios and Uniphy IP was used for DDR2 RAM.

What should I do?

 Warning (14285): Synthesized away the following RAM node(s):

  Warning (14320): Synthesized away node "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_s0:s0|rw_manager_ddr2:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|q_b[8]"

 Warning (15055): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

 Info (15024): Input port INCLK[0] of node "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is driven by clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl which is OUTCLK output port of Clock control block type node clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl

Warning (15058): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[1] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins

Warning (169064): Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results

 Info (169065): Pin memory_mem_ck[0] has a permanently enabled output enable

 Info (169065): Pin memory_mem_ck_n[0] has a permanently enabled output enable

Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs.

[EricMunYew_C_Intel]

Hi, Xiaoqiang

You may refer to below:

Warning (14285): Synthesized away the following RAM node(s):

 Warning (14320): Synthesized away node "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_s0:s0|rw_manager_ddr2:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|q_b[8]"

The q_b[8] may be not in usage, and therefore it is synthesized away.

Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs.

The configuration pins have to be at the same voltage level, may be you need to check if the VCCIO of all the configuration pins are at the same voltage level. Alternatively, you can allocate all the configuration pins under one IO bank which has one voltage level.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Xiaoqiang

Warning (169064): Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results

 Info (169065): Pin memory_mem_ck[0] has a permanently enabled output enable

 Info (169065): Pin memory_mem_ck_n[0] has a permanently enabled output enable

Pin memory_mem_ck[0] and pin memory_mem_ck_n[0] are either have no output enable, or they are VCC and GND enable.

If you enable them later, it will change your fitting result. You may want to add an output enable that is not GND/VCC to them.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Xiaoqiang

 Warning (15055): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

 Info (15024): Input port INCLK[0] of node "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is driven by clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl which is OUTCLK output port of Clock control block type node clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl

Warning (15058): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[1] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins

You may want to check if INCLK[0] is a dedicated clock input pin.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Xiaoqiang

Can we close the case if you have no more question ?

Thanks.

Eric