What does the APPS core in PCIe Example Design Do

[corestar]

This is my first attempt at using PCIe in a Cyclone V using Quartus 19.1 Lite. I'm using the Cyclone V SoC Development kit. I loaded the example design:

     hip_cv_x1_g1_ast64_140.qar

to attempt to understand the Avalon streaming core. This example design, as well as all others I've looked at, creates an APPS core. But I can't find any documentation of any kind of what the APPS core does. It's sort of key. Some APP notes say to modify the APPS core for our app. How? Where is it? What does it do?

Appreciate any help.

[wchiah]

Hi,

For further information about APPS you can refer document below

https://cdrdv2-public.intel.com/655090/ug-01110-1_5.pdf

at page 25/288 it mention how this root port BFM configures the DUT.

Regards,

Wincent_intel

[corestar]

Hello,

Yes, I had seen that. But I'm afraid it does not tell you how APPS works. Changing parameters in a "black box" APPS does not really help me to create my own system.

On page 17 it says APPS should have a altpcied_sv_hwtcl.v file associated with it, but I cannot find that anywhere in the install or online.

Thanks

[wchiah]

Hi,

Can I understand more what you want to achieve ?

If i see the description the APPS is application for Avalon Streaming HIP.

Where for AVST detail , you may refer to guide below

https://www.intel.com/programmable/technical-pdfs/683524.pdf

Regards,

Wei Chuan

[corestar]

Hello @wchiah ,

I'm prototyping a system that uses the PCIe Gen2 x1 interface on a Rasperry Pi Compute Module 4 connected to a Cyclone V SoC Eval board (I'm not using the HPS, just the fabric). The initial goal is to just have the PI see the FPGA PCIe endpoint. This would confirm the hardware is working and the PCIe IP in the FPGA is booting correctly (eg all resets). The equivalent of a PCIe "Hello World"

Then I would progressively add features to read/write data between the PI and FPGA.

I am of course reading the PCIe docs, but a useful example would be helpful. The docs you mention do not actually explain how the APPS core works.  It's just a black box. So it does not help me write my own application. There are many signals APPS handles (resets, power, MSI .....) and it would be useful to have the source code for it.

A useful example would just create the  PCIe Hard IP core, and transceiver reconfig core in Qsys, and export the signals a user app has to deal with to a top level design and provide HDL source code for how to handle all those signals. 

Thanks

[wchiah]

Hi,

Unfortunely, we does not provide any source code for it.

But if you are using Cyclone V SoC eval board.

You may refer to link below

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-sx.html

We do provide all the example including Memory, XCVR, GPIO and PCIe 1.0 x4

Regards,

Wincent_Intel

[corestar]

Hello @wchiah ,

I had been using those examples as well (eg the ep_gen1x4_22.1_balanced). They are somewhat helpful (no APPS or other black boxes in Qsys), and have a toplevel that shows how to connect to some of the QSYS outputs. It sort of shows how to handle resets.  But the examples seem to be full of bugs, so I'm not sure how much I trust them. For example, the they do not meet timing and drive lines that are outputs. For example, reconfig_mgmt_readdata is an output from Qsys, but they drive it to zero. Many of the pins are assigned locations that do not exist (eg the pcie_rx  and pcie_tx, pcie_refclk). The examples were clearly never actually run.

I ordered a Terasic board that seems to include useful examples. Includes Linux driver and application,  and Quartus FPGA project (not just a .qsys file). There is a Qsys system, but no black boxes.Hopefully, it will help. The Linux driver is from Altera, but apparently from a Wiki that no longer exists.

I'll give a shot and hopefully get things working.  You seem pretty knowledgeable about PCIe if I have more specific questions :-). 

Thanks

[wchiah]

Hi,

Unfortunately, we does not have much step by step example for all the pin assignments.

Because all of the application is quite different, user needs to define what they need to assign themself.

You may check the pin guidance at below

https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html

If you need a step by step guidance, we do provide some of the video for cyclone V

https://www.intel.com/content/www/us/en/support/programmable/support-resources/fpga-training/fpga-quick-video-index.html?q=cyclone%20v&s=Relevancy

I am not sure which pcie_refclk that you are looking at, but we do provide the schematic for connection guidance.

Which is good to be refer to.

https://www.analog.com/media/en/technical-documentation/eval-board-schematic/c5_soc_devkit_c.pdf

Also, the example design are strictly for reference purpose only, it might not include what you needed in total.

For the linux driver for Cyclone V, you may refer to

https://www.rocketboards.org/foswiki/view/Documentation/LinuxDrivers

Hope that answered your question. Please let me know if you need more information.

Regards,

Wincent_Intel

[corestar]

Hello @wchiah 

Unfortunately, we does not have much step by step example for all the pin assignments.

Because all of the application is quite different, user needs to define what they need to assign themself.

...

This was not just a generic example, it came with the Cyclone V Soc Development Kit CD. It seemed reasonable to assume it would actually work with the kit. That's the point of an example :-). It even included a .sof file (ep_gen1x4_22.1.sof). What board is that for if not the the one it came with?

But I'm quite familiar with Quartus and had no problem setting the pins correctly. But there were other issues such as the example driving ports that are outputs.

I've accepted the fact that useful examples are a lost art. It's not just Intel.

Thanks anyway.

[wchiah]

Hi,

Thanks for your feedback, What the best I can help at the moment is to submit an internal ticket to related team.

Hope they will work on include useful examples. Includes Linux driver and application and some of the example connection for the APPS core.

Do you still have any further question that I can help you more ?

Regards,

Wincent_Intel

[corestar]

@wchiah 

Hopefully they will improve the examples. I don't have any further questions at the moment.

A useful example would show how to read and write to a buffer in user fabric either initiated by processor or FPGA.

I've checked many examples, including Arria 10 and Cyclone 10, and none show how the user FPGA code can do things such as:

1. Initiate a transfer from a buffer on the processor
2. Know when the processor has written data to a buffer on the FPGA
3. Send and interrupt from the FPGA to the processor

These are things all users, regardless of application, would need to know. They all have the same black APPS.

Thanks

[wchiah]

Hi,

Unfortunately, Cyclone V consider a legacy device.
Hence the example might not be as complete as other new devices.

If you need to develop something for business use, I would recommend you to look at our latest product 
https://www.intel.com/content/www/us/en/products/details/fpga/agilex.html
You may contact Intel distributor in your region if you would like to know more
https://www.intel.com/content/www/us/en/partner/showcase/partner-directory/distributor.html#sort=relevancy

Please accept my apology for cannot help much regarding your queries.
Regards,
Wincent_Intel

[corestar]

Hello @wchiah 

I'm afraid a $40,000 Agilex chip will not work for our application :-). Our Arrow rep assured us the Cyclone V would not EOL before 2032. I assume that is still valid? The Arria 10 is a possibility, but the prices of those has doubled as well.

I'll figure it out. I have the Linux side working with a PCIe driver (which I had assumed would be the hard part) for a simple PCIe RS-232 card. So with enough effort, I'll figure out the FPGA side.

Thanks

Begin irrelevant side notes:

One thing I wondered about is why in the world they did not simply integrate the XVR Reconfig Controller and its driver into the PCIe Hard IP core. Made no sense. Looking at the Arria 10, they appear to have done exactly that.

Not your fault they don't have useful examples or appear to even understand the concept of a useful example. It's odd since the Altera online training was always superb and Quartus is vastly superior to Xilinx (which I used for many years) and Vivado. But the PCIe training was not useful.

I first moved to Altera from Xilinx because their JESD204b core was incomprehensible, but without ever having used Quartus, got it running in a few days with Altera tools. Same with Ethernet and many other projects. But for some reason, they decided to make PCIe difficult.

End of irrelevant side notes:

[wchiah]

Hi,

Thanks for your feedback, It is valuable to us. 
Happy that you feel Altera training is useful. 
For the PCIe, there is some resource I wish to share with you
https://www.intel.sg/content/www/xa/en/support/programmable/support-resources/design-guidance/pcie-support.html?countrylabel=Asia%20Pacific

there is quite a lot resource available there, hope that is helpful to you.

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case since the last reply.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

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Regards,

Wincent_Intel