- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We are a small business startup evaluating the the viability of using Altera lower cost FPGAs for small scale production, probably focusing on MAX 10 FPGA, Cyclone IV E, and/or Cyclone V A9. We are using VHDL. One issue is the possible use of (some, if any) IP in production without buying a license. Any IP available for free use in production? (We already know that some IP can be evaluated for free, but need paid licences in production.)
We have already established that VHDL 2008 will not be available in the Quartus Lite version, so no cores depending on that is usable for us now.
Thanks.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I tested a bit in Quartus Prime Light (20.1.1) for a MAX10 (10M50DA type), and these are some findings.
- It seems it's the more elaborate IPs that needs paid licenses (as has been said), so PLLs, use of ADC in MAX10, etc. are free
- You can disable use og Evaluation licenses:
Assignments > Settings > Compilation Process Settings > More Settings > Intel FPGA IP Evaluation Mode: Disable
- In the Compilation Report you can check (examples when disabled):
- Assembler > Encrypted IP Cores Summary (Gives for example: Nios II Embedded...: Unlicensed; Signal Tap: Licensed)
- Assembler > Messages (gives for example)
- 115003 Can't generate programming files ... not valid license for following IP core(s)
115005 Unlicensed IP: "Nios II Embedded Processor Encrypted output..."
115004 Unlicensed encrypted design file: "c:/....../altera_nios_gen2_rtl_module.sv"
- When Evaluation mode is Enabled, you get the programming file <name>_time_limited.sof (as Frank said earlier).
- You can also check in the Compilation Report
- Analysis & Synthesis > IP Cores Summary, the Licence Type column
For example: Signal Tap: Licensed; no licence needed (it seems): N/A, Nios II Embedded...: OpenCore (not free)
(Nios II is btw outdated, Nios V should be used for new designs, but it needs a paid license as well.)
So, I'm a bit more optimistic, seems that much of the simpler IP in Platform Designer in Quartus can be used.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
In Lite, you don't really get anything without paying for it. https://www.intel.com/content/www/us/en/products/programmable/intellectual-property/ip-base-suite.html
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Does that mean you can't use the PLLs, ADs etc. in MAX 10 run in production without paying for IP?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I don't know what the differentiators are, but basic hardware operations like PLLs and ADC and such are always available. It's the add-on functional IP where licensing starts.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks. Is there a way I can see in Quartus Lite what is add-on functional IP and what counts as basic hardware operation?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
No. I always joke that they should put little dollar signs next to the IP that requires licensing.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
IP that needs a payed license is e.g. CIC Filter, FFT, NCO, Ethernet MAC. It shows by generating only time-limited .sof in Quartus lite and no other programming files.
Regards
Frank
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yeah, but you've got to go through actually creating and generating the IP to find that out.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Frank. Then you get a warning, at least. And at the end of the process, as sstrell say... I guess it might be asking too much to get that information earlier, e.g. before you start investing time in the IP... So, do a mock generation to root out if it's an expesive dude you're dealing with?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I tested a bit in Quartus Prime Light (20.1.1) for a MAX10 (10M50DA type), and these are some findings.
- It seems it's the more elaborate IPs that needs paid licenses (as has been said), so PLLs, use of ADC in MAX10, etc. are free
- You can disable use og Evaluation licenses:
Assignments > Settings > Compilation Process Settings > More Settings > Intel FPGA IP Evaluation Mode: Disable
- In the Compilation Report you can check (examples when disabled):
- Assembler > Encrypted IP Cores Summary (Gives for example: Nios II Embedded...: Unlicensed; Signal Tap: Licensed)
- Assembler > Messages (gives for example)
- 115003 Can't generate programming files ... not valid license for following IP core(s)
115005 Unlicensed IP: "Nios II Embedded Processor Encrypted output..."
115004 Unlicensed encrypted design file: "c:/....../altera_nios_gen2_rtl_module.sv"
- When Evaluation mode is Enabled, you get the programming file <name>_time_limited.sof (as Frank said earlier).
- You can also check in the Compilation Report
- Analysis & Synthesis > IP Cores Summary, the Licence Type column
For example: Signal Tap: Licensed; no licence needed (it seems): N/A, Nios II Embedded...: OpenCore (not free)
(Nios II is btw outdated, Nios V should be used for new designs, but it needs a paid license as well.)
So, I'm a bit more optimistic, seems that much of the simpler IP in Platform Designer in Quartus can be used.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page