altera_mem_if_ddr3_emif

[NGord]

Hi

altera_mem_if_ddr3_emif used to have a parameter box 'enable afi half rate clock' in Quartus 18

Somewhere between V18 and V23 it has disappeared and I cant get afi_half_clk to work any more.

How do I enable afi_half_clk in V23?

[NGord]

If opening Platform designer with no Project selected , I see the 'half-rate' tick box in DDR3 SDRAM Controller with UniPHY Intel FPGA IP, regardless of Quartus version.
If the  project is for a MAX10, the tick box disappears and I have no afi_half_clk.
I can find no explanation for this.

[NGord]

Is the issue that the MAX10 PLL doesnt have enough PLL outputs?

[AdzimZM_Intel]

Hi NGord,

For Max 10 FPGA device, the DDR3 EMIF IP doesn't support afi half rate clk.

I think the Cyclone V device is used by default if no project is opened.

Therefore, the DDR3 EMIF IP is targeting to Cyclone V and you may see the afi half rate clock option.

Regards,

Adzim

[AdzimZM_Intel · Accepted solution]

Hi @NGord 

Do you have any further question in this thread?

Regards,

Adzim