connection_between_msgdma_and_OCM

[SERMASWATHIKA]

Hi Team,

    i am upgrading the design from 13.1 to 22.1. in my design i have ethernet ip , in 13.1 ethernet is handled SGDMA with OCM. In 22.1 SGDMA ip is available, but while generating bsp , it is not supporting. So i am changing the sgdma ip to msgdma ip.

  in 13.1 version, sgdma is connected with ocm like this,

sgdma descriptor read and write(avalon master) is connected to ocm slave. But in msgdma descriptor slave is the avalon slave. How i can connect the msgdma descriptor slave to OCM . I got confused in this connection.

Please guide me to resolve this issue.

[EBERLAZARE_I_Intel]

Hi,

Is this design from the "Simple Socket Server"? Or is the design your own?

Is it using the Nios II processor or the HPS?

[SERMASWATHIKA]

Hi,

  our own design..it has nios II processor .

  Please give solution for this asap, because project work depends on this

[SERMASWATHIKA]

PLease give response for this..how to connect the msgdma descriptor to OCM since both avalon is slave..please give solution for this

[JingyangTeh]

Hi

I will be taking over this case from Eber.

Sorry for the late reply.

There is an example for connection between the MSGDMA to OCM in the example below:

Agilex™ 7 FPGA - Nios® V/m Processor with DDR DMA and OCM Design Example (intel.com)

Regards

Jingyang, Teh

[SERMASWATHIKA]

Hi,

 Thanks for your response i will check that.

  i want to confirm that sgdma support is there or not.

 why bsp is generating mSGDMA library files in firmware even FPGA qsys design contains sgdma ip (sopcinfo).

 We faced this issue. after that only we moved to msgdma ip use.

 Whether we are moving in right direction. Please confirm this.

[SERMASWATHIKA]

Hi ,

  Thanks for sharing the reference design.

 Can you share the reference design which has ethernet interface using msgdma and ocm ? we are trying to implement the TSE with msgdma

[JingyangTeh]

Hi

Sorry for the late response.

SGDMA is still supported. The example design shared is using mSGDMA instead of SGDMA.

That is why u are seeing mSGDMA BSP files generated.

Currently there is no example design for connection between the TSE and mSGDMA.

There is only design for the TSE only in link below:

https://www.intel.com/content/www/us/en/design-example/776159/intel-arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh