problem about reset of FFT IP

[Altera_Forum]

Hello,every one! 

I have some problem about reset of FFT IP. In my project,reset of FFT IP is connected with Nios output; Nios output clock is 62MHz; FFT IP work error sometimes even at 80MHz and 130MHz; Then I think there is something wrong about the reset signal, try to insert a register between reset and Nios output, FFT IP works well. I want to know whether FFT IP deal with the reset signal. When I use the IP, How I deal with the reset signal.

[Altera_Forum]

your nios clk is 62MHz, fft clk is 80 or 130 ? 

in either case, your nios clk canot be synchronisd edge on edge to fft clk. Your post suggests as if you are having recovery/removal timing violation. But such violation is unlikely to cause persistent problem like yours.   As far as reset is concerned, the proper way is to register the reset through two registers clked by fft clk to filter off any possible metastable states and that is enough.   If the problem persists then it is not the reset between two clk domains to blame.