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timing_error_for_pll_afi_clock_on_ddr3_ip_controller

SERMASWATHIKA
New Contributor I
1,419 Views

Hi Team,

  I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces.

pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board.

 Nios processor also connected with afi clock only (200 Mhz)

For this design , i am getting pll_afi_clock setup time violation.

i have attached the timing report. 

PLease give solution for this.

 

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18 Replies
TingJiangT_Intel
Employee
1,339 Views

The setup violations showed in the report are all asynchronous path. You can use 'set clock group' constraint to eliminate the relationship between 'inst|ddr3|pll0|pll_dq_write_clk ' and 'dqs_n[3]_OUT'.


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SERMASWATHIKA
New Contributor I
1,305 Views

Hi Ting,

  I have added constraint for the clocks like you have mentioned, but still facing the timing violation error:

SERMASWATHIKA_0-1712575959155.png

could you please give suggestions whether this constraints are okay?

 

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TingJiangT_Intel
Employee
1,288 Views

You don't need to constraint all the clocks, just apply it to the clocks of asynchronous path( the launch and latch clock ).

BTW you can try to apply the following constraint:

'derive_pll_clocks'


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SERMASWATHIKA
New Contributor I
1,276 Views

Hi ,

  I have tried with derive_pll_clock also. but still facing timing violation issue.

SERMASWATHIKA_0-1712667676162.png

do i miss anything?

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TingJiangT_Intel
Employee
1,245 Views

You mean the same violation still exits? Could you show the violation in the timing analyzer which is better to view.

BTW why you put the altera_reserved_tck in the group? I think you don't need to constraint it.


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SERMASWATHIKA
New Contributor I
1,234 Views

Hi,

for better view, i have attached the screenshot of violation

SERMASWATHIKA_0-1712837149031.pngSERMASWATHIKA_1-1712837226500.png

 

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TingJiangT_Intel
Employee
1,128 Views

There are also synchronization path violation. Could you please provide your project for further analysis.


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SERMASWATHIKA
New Contributor I
1,118 Views

Hi,

  i have attached the project archive with this response. Please let me know if you have any query on this. please give solution for this violation

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TingJiangT_Intel
Employee
969 Views

Hi there, I can't open timing analyzer with the project you provided. Could you provide the project which has completed the compilation process?

Please provide all the files of the project, and you can exclude you RTL(.v file) for confidentiality.

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SERMASWATHIKA
New Contributor I
830 Views

ok , i will send the project files which is compiled within today

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TingJiangT_Intel
Employee
849 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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SERMASWATHIKA
New Contributor I
830 Views

Hi,

   sorry for the delay response. i will send the project archive today. please reopen the ticket.

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RichardTanSY_Intel
740 Views

Try reduce the number of logic levels to 2-3 by adding pipeline register (this will add latency in your design).

As higher logic level will increase delay on the critical path. 

RichardTanSY_Intel_0-1714031344205.png

You may checkout this video on @16.49 minute marks

https://www.youtube.com/watch?v=UGGkKZylJBo

 

Regards,

Richard Tan 

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SERMASWATHIKA
New Contributor I
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RichardTanSY_Intel
522 Views

Do you able to close timing?


Regards,

Richard Tan


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SERMASWATHIKA
New Contributor I
400 Views

Hi,

  No still i am working on it..but for me timing violations are showing within the ip files. i cant modify the rtl path , so need assistance for this.

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TingJiangT_Intel
Employee
65 Views

Hi there, what violation you get, could you please share the path in timing analyzer.


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SERMASWATHIKA
New Contributor I
18 Views

Hi,

I am getting timing violation for these path

SERMASWATHIKA_0-1715940246681.png

 

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