timing_error_for_pll_afi_clock_on_ddr3_ip_controller

[SERMASWATHIKA]

Hi Team,

  I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces.

pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board.

 Nios processor also connected with afi clock only (200 Mhz)

For this design , i am getting pll_afi_clock setup time violation.

i have attached the timing report. 

PLease give solution for this.

[TingJiangT_Intel]

The setup violations showed in the report are all asynchronous path. You can use 'set clock group' constraint to eliminate the relationship between 'inst|ddr3|pll0|pll_dq_write_clk ' and 'dqs_n[3]_OUT'.

[SERMASWATHIKA]

Hi Ting,

  I have added constraint for the clocks like you have mentioned, but still facing the timing violation error:

could you please give suggestions whether this constraints are okay?

[TingJiangT_Intel]

You don't need to constraint all the clocks, just apply it to the clocks of asynchronous path( the launch and latch clock ).

BTW you can try to apply the following constraint:

'derive_pll_clocks'

[SERMASWATHIKA]

Hi ,

  I have tried with derive_pll_clock also. but still facing timing violation issue.

do i miss anything?

[TingJiangT_Intel]

You mean the same violation still exits? Could you show the violation in the timing analyzer which is better to view.

BTW why you put the altera_reserved_tck in the group? I think you don't need to constraint it.

[SERMASWATHIKA]

Hi,

for better view, i have attached the screenshot of violation

[TingJiangT_Intel]

There are also synchronization path violation. Could you please provide your project for further analysis.

[SERMASWATHIKA]

Hi,

  i have attached the project archive with this response. Please let me know if you have any query on this. please give solution for this violation

[TingJiangT_Intel]

Hi there, I can't open timing analyzer with the project you provided. Could you provide the project which has completed the compilation process?

Please provide all the files of the project, and you can exclude you RTL(.v file) for confidentiality.

[SERMASWATHIKA]

ok , i will send the project files which is compiled within today

[TingJiangT_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[SERMASWATHIKA]

Hi,

   sorry for the delay response. i will send the project archive today. please reopen the ticket.

[RichardTanSY_Intel]

Try reduce the number of logic levels to 2-3 by adding pipeline register (this will add latency in your design).

As higher logic level will increase delay on the critical path. 

You may checkout this video on @16.49 minute marks

https://www.youtube.com/watch?v=UGGkKZylJBo

Regards,

Richard Tan 

[SERMASWATHIKA]

ok i will check this and let you know