Agilex 7 AGF027 FPGA 2x F-tile pcie IP system pll clock not working

[Zefu]

Hello, 

We have an Intel Agilex 7 fpga dev kit from Intel, which features an AGFB027R24C FPGA (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf027-and-agf023.html). We implemented a design with 2x F-Tile PCIE IPs, where one F-Tile is configured as 4x4 upstream PCIe ports, and the other is 4x4 downstream ports. Both running at Gen3 speed. We implement two FTile systemplls, one for each F-Tile PCIE IP. The system plls generate ref-clks to the PCIe IPs. 

None of the 8 PCIe ports are able to show a link-up status, although we do have them connected to different PC hosts and PCIe SSD card.

The 4x4 upstream ports are able to get out of the reset and the system pll seems to lock from the signaltap. However, the 4x4 downstream ports are always in reset and the lock signal of the system pll is never raised.

I have double checked the IO pin locations for the system plls and the perst_n to the PCIe IP. Didn't find any issue there.

Any suggestion is greatly appreciated.

Below are the constraints on the pin locations of the ref-clk inputs to the two system plls

  29 set_global_assignment -name DEVICE AGFB027R24C2E2VR2
  30 set_global_assignment -name FAMILY "Agilex 7"
  31 set_location_assignment PIN_BR7 -to i_fpga_downstream_RefClk_3
  32 set_location_assignment PIN_CD8 -to i_fpga_downstream_RefClk_5
  33 #set_location_assignment PIN_BU7 -to "i_fpga_downstream_RefClk_3(n)"
  34 #set_location_assignment PIN_CC7 -to "i_fpga_downstream_RefClk_5(n)"
  35 set_instance_assignment -name IO_STANDARD HCSL -to i_fpga_downstream_RefClk_3 -entity Chip
  36 set_instance_assignment -name IO_STANDARD HCSL -to i_fpga_downstream_RefClk_5 -entity Chip
  37 set_location_assignment PIN_CG13 -to i_fpga_downstream_Reset_n
  38 set_instance_assignment -name IO_STANDARD 1.8V -to i_fpga_downstream_Reset_n
  39 set_location_assignment PIN_BC49 -to i_fpga_upstream_RefClk_p0p2
  40 set_location_assignment PIN_AD48 -to i_fpga_upstream_RefClk_p1p3
  41 #set_location_assignment PIN_BE49 -to "i_fpga_upstream_RefClk_p0p2(n)"
  42 #set_location_assignment PIN_AC49 -to "i_fpga_upstream_RefClk_p1p3(n)"
  43 set_instance_assignment -name IO_STANDARD HCSL -to i_fpga_upstream_RefClk_p0p2 -entity Chip
  44 set_instance_assignment -name IO_STANDARD HCSL -to i_fpga_upstream_RefClk_p1p3 -entity Chip
  45 set_location_assignment PIN_BR43 -to i_fpga_upstream_Reset_n
  46 set_instance_assignment -name IO_STANDARD 1.8V -to i_fpga_upstream_Reset_n

 Zefu

[RongYuan]

Hi Zefu,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Your upstream port is on bank 12C. You can generate an example design using Gen4 1x16 for this bank and try if host can recognize by lspci. Set PCIe speed in host BIOS to AUTO or Gen4.  

Regards,

Rong

[RongYuan]

This case is set to close.

Regards,

Rong