Arria 10 Gx board, SFP connection no link

[TSchu3]

Hello all, I am attempting to bring up a link on a new Arria 10 Gx board, using the SFP+ connector.  I started by generating an example design for the Low Latency Mac, with the 1G/2.5G Ethernet Example Design preset.  This also generated a PHY, 1G/2.5G/5G/10G Multi Rate Ethernet PHY.

When I load this design on the board and connect it to a switch I can see 2.5G link lights.  However, I cannot see a link established on the PHY port for LED_Link, I can also observe that rx_is_locked_to_data is constantly going up and down. 
The Tx side is showing ready.
If I plug the cable in to a 1Gig switch I get no lights on the switch and the same results on the signal tap.
If I leave the cable unplugged I still see the same behavior on the signal tap.

I tried the included Board example design qts_com.  which includes an SFP connection and I see the same behavior.

I don't have any idea what is going wrong here.  I am sending in the correct Reference Clock to the example design of 125Mhz.

Any help troubleshooting this would be greatly appreciate.


Thank you!

[ZiYing_Intel]

Hi,

Can you share your .qar file here?

Best regards,

zying

[TSchu3]

Hello, I have attached two example projects that I believe should bring up a link on the Arria 10 GX board, neither do.

qts_com_23_2_0_94 is from the example projects that come with the dev board files.

LL10G_10G_USXGMII  is generated from the platform designer for the Low Latency 10G mac.  I have manually assigned pins to it for the Arria 10 board.   It also fails to bring up a link.

I am using the SFP+ connector.

Thanks again for any advice.

[ZiYing_Intel]

Hi,

May I know that you are using which type SFP+ connector?

Best regards,

zying

[TSchu3]

Hi, I am currently using a TP LINK TL-SM5310-T  module for the SFP+.

Thanks

[TSchu3]

Hello,  Are there any further questions I can answer?
I really just need a simple example design of a PHY that will bring up a link on this board.  It does not have to be one of the projects I sent.  Any other project that is functional should work.
I am trying to get this dev board operational and time is of the essence.

Thanks

[ZiYing_Intel]

Hi,

Could you try this example design?

https://www.intel.com/content/www/us/en/design-example/784689/intel-arria-10-fpga-10gbase-kr-phy-ip-design-example.html

For more example design, you may go to our FPGA Design Store https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?q=niosV&s=Relevancy

Best regards,

zying

[TSchu3]

Hello, I tried out the example design at
https://www.intel.com/content/www/us/en/design-example/784689/intel-arria-10-fpga-10gbase-kr-phy-ip-design-example.html

It failed to bring up a  link at either 1G or 10G.  Were you able to establish a link with this design for the Arria10 GX dev board? 
If so please send me your archived project.

The only changes made to the example design were the pinouts to match the Dev board.

I am still in need of an example PHY that can bring up a link on this board using the SFP+ connector.

Thanks

[ZiYing_Intel]

Hi,

Could you try to do internal loopback on the device to check whether the device can function normally?

Best regards,

Zi Ying

[TSchu3]

Hello, I have had  success in getting the LL10G_10G_USXGMII example project (posted earlier) to connect.
I had to turn off USXGMII Mode and revert to 10GBase-R mode.  I am not sure why this affected the link but it allowed me to proceed.
I am now able to send and receive data at 1G speeds.

I have one remaining issue.  The internal PHY port 'operating_speed'  always shows as "000" which I believe corresponds to at 10G connection.  This is true even when I am connected to 1G or 2.5 G only devices.  So it is not updating to the correct current speed.

How can I get reliable information from the PHY internally about its current connection speed?  I do not see a register that I can read which will tell me this information.  How can I limit the allowed connection speeds?  For example, If I cannot run at 10G speeds I do not want the PHY to be able to connect to 10G only devices.

Thanks

[ZiYing_Intel]

Hi,

Can I get more clarification about this "The internal PHY port 'operating_speed' always shows as "000" which I believe corresponds to at 10G connection. This is true even when I am connected to 1G or 2.5 G only devices. So it is not updating to the correct current speed."?

May I know that you how to debug it? Do you just change the speed through the different switch that connect to the board?

Best regards,

Zying

[ZiYing_Intel]

Hi,

Is there any update from you?

Best regards,

zying

[TSchu3]

Hello,  using signal tap I monitor the 'operating_speed' port.
If I plug the dev board into a 1G only capable device.  The link comes up and I can send data across the link.
However the 'operating_speed' port still shows '000' which means 10G.
I get the same result if I plug it into a 2.5G only switch or a 10G only switch.  The port always reads 10G.

I am not doing anything internally to the PHY.  This is all automatic.  It should tell me what speed it is connected at.  I would have no other way of knowing the speed from the FPGA fabric perspective.

Thanks

[ZiYing_Intel]

Hi,

May I know that currently you are using USXGMII Mode or 10GBase-R mode?

Best regards,

zying

[TSchu3]

I am using 10GBase-R mode.  USXGMII mode could not establish a link at any speed.

[ZiYing_Intel]

Hi,

If currently you are using 10GBase-R mode, I think that's why you always getting "000" in your operating speed port because your default value is 10G already.

Could you try to change the USXGMII speed by changing the PHY register value manually? And then you can check the output of the port whether got any changes.

To change the PHY register value, you may refer to the Section 2.6.5.4.2. Configuration Registers, Table 160. PHY Register Definitions, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/configuration-registers-82795.html

For further information about the operating speed, you may refer to Section 2.6.5.5.2. Operating Mode and Speed Signals, Table 162. Transceiver Mode and Operating Speed Signals, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/operating-mode-and-speed-signals.html

Best regards,

Zi Ying

[TSchu3]

As stated in my last response-  changing to USXGMII results in no link.  It is not working.

I want to know what the current speed is.  As stated already I am plugged into 1G devices.  It is impossible to be connected at 10G.

How do I determine the current operating speed,  not the default speed?


This is exactly what I am asking about.  It always states that the Operating speed is 10G.
"For further information about the operating speed, you may refer to Section 2.6.5.5.2. Operating Mode and Speed Signals, Table 162. Transceiver Mode and Operating Speed Signals, https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/operating-mode-and-speed-signals.html"

[ZiYing_Intel]

Hi,

Could you provide your current .qar file? So that I can have a look into the ip settings.

Best regards,

zying

[ZiYing_Intel]

Hi,

How do I determine the current operating speed, not the default speed?

>> In 10GBase-R MAC mode the MAC works with different speed just by repeating the same bit value for the duration of the speed. You can get the speed info from the input clock, as Phy line speed is aligned with the input clock.

i.e., 1G output it repeats 10 cycles same bit value on the 10G link and there is change in the PHY line speed.

Same is the case in 2.5G mode MAC manipulates the data to achieve 2.5G (4 clock cycles of same bit value and by reading the PHY speed it will result 10G but the MAC does the change in speed)

Best regards,

zying

[TSchu3]

Thank you, this is very interesting.  How does the MAC know that the data is/should be repeated and how often?  the 'operating speed' signal is supposed to send this information to the MAC.  If it always says 10G, then how would the MAC know it was really sending repeated 1G data, for example?

Is this information stored somewhere in a MAC register?
How can I gain access to it?

[ZiYing_Intel]

Hi,

I will send the design for you as reference design through email. Our design team tested the A10 LL10G_Usxgmii_design on hardware in QPDS23.2 and the USXGMII is working for them.

Channel 0: all speeds passed

Please do let me know if you haven't received the email.

Best regards,
zying