We are currently developing a project based on the BeMicroMAX10 evaluation board from Arrow.
However, we are experiencing some inconsistencies in the MAX10 ADC. We have configured the FPGA with 5 analog inputs, and we can read them. However, the readings present a constant offset that is not negligible.
In this test, Vin (0 to 50V) is scaled down (range 0 to 2.5 V) to feed 3 analog inputs. Then, readings are scaled up to obtain 1:1 ratio. The same voltage feeds the 3 inputs, there is only one power supply. Similar tests have been performed with only one analog input, while holding the other 4 analog inputs to ground.
We have noticed that in the BeMicroMAX10 schematics (https://static5.arrow.com/pdfs/2014/11/26/1/24/3/371/arrowd_/manual/bemicro_max_10-schematic_a4-2014...) the ADC is properly powered:
but the VCCIO1A bank is powered to 3V3:
And also, the ADC1IN5 is connected to 3V3:
According to the Intel MAX 10 FPGA Device Family Pin Connection Guidelines
it looks like the evaluation board is out of spec, as
- A) VCCIO1A is not 2.5 V, but 3.3 V,
- B) ADC1IN5 is above 2.5V
We were wondering if this could be the ultimate cause of the offset that we are experimenting, and, if any, we could do anything to circumvent this issue.
Thank you very much
We don't have insight on how the connection been decided and what characterization had been carried out on 3rd party's Evaluation board.
Can you check directly with the vendor on the board connection?