Can't get SRAM IDT71V416 work on Nios II dk Stratix II edition

Altera_Forum · ‎03-19-2008

Hi to all,

If I use the standard IDT71V416 controller on a niosII_stratixII_2s60ES development board (two chip in parallel for 32 bit data bus) it works well.

But with my custom controller compliant to datasheet (tcl code follows) I get "verify failed" in execution but the memory test (MemTest) works great.

Can anyone help?

Thank you.

# TCL File Generated by Component Editor 7.2sp1 on:

# Wed Mar 19 14:53:42 CET 2008

# DO NOT MODIFY

# Blackbox -- The top level is not based on an HDL file

set_source_file ""

set_module "idt71v416"

set_module_description ""

set_module_property "editable" "true"

set_module_property "group" "User Logic"

set_module_property "instantiateInSystemModule" "false"

set_module_property "version" "1.0"

# Module parameters

# Interface global_signals_clock

add_interface "global_signals_clock" "clock" "sink" "asynchronous"

# Ports in interface global_signals_clock

add_port_to_interface "global_signals_clock" "clk" "clk"

set_port_direction_and_width "clk" "input" "1"

add_port_to_interface "global_signals_clock" "reset_n" "reset_n"

set_port_direction_and_width "reset_n" "input" "1"

# Interface avalon_tristate_slave_0

add_interface "avalon_tristate_slave_0" "avalon_tristate" "slave" "global_signals_clock"

set_interface_property "avalon_tristate_slave_0" "isNonVolatileStorage" "false"

set_interface_property "avalon_tristate_slave_0" "readLatency" "0"

set_interface_property "avalon_tristate_slave_0" "readWaitStates" "10"

set_interface_property "avalon_tristate_slave_0" "holdTime" "0"

set_interface_property "avalon_tristate_slave_0" "printableDevice" "false"

set_interface_property "avalon_tristate_slave_0" "readWaitTime" "10"

set_interface_property "avalon_tristate_slave_0" "setupTime" "0"

set_interface_property "avalon_tristate_slave_0" "writeWaitTime" "10"

set_interface_property "avalon_tristate_slave_0" "timingUnits" "Nanoseconds"

set_interface_property "avalon_tristate_slave_0" "minimumUninterruptedRunLength" "1"

set_interface_property "avalon_tristate_slave_0" "activeCSThroughReadLatency" "false"

set_interface_property "avalon_tristate_slave_0" "isMemoryDevice" "true"

set_interface_property "avalon_tristate_slave_0" "writeWaitStates" "10"

set_interface_property "avalon_tristate_slave_0" "maximumPendingReadTransactions" "0"

# Ports in interface avalon_tristate_slave_0

add_port_to_interface "avalon_tristate_slave_0" "data" "data"

set_port_direction_and_width "data" "bidir" "32"

add_port_to_interface "avalon_tristate_slave_0" "addr" "address"

set_port_direction_and_width "addr" "input" "18"

add_port_to_interface "avalon_tristate_slave_0" "cs_n" "chipselect_n"

set_port_direction_and_width "cs_n" "input" "1"

add_port_to_interface "avalon_tristate_slave_0" "oe_n" "read_n"

set_port_direction_and_width "oe_n" "input" "1"

add_port_to_interface "avalon_tristate_slave_0" "we_n" "write_n"

set_port_direction_and_width "we_n" "input" "1"

add_port_to_interface "avalon_tristate_slave_0" "be_n" "byteenable_n"

set_port_direction_and_width "be_n" "input" "4"

Altera_Forum · ‎03-21-2008

Ok, I resolved with the help of user Fischer from Niosforum.

The controller doesn't understand a address setup time of 0ns: at least 1ns is needed despite what the datasheet says.

Thanks to all

Altera_Forum · ‎03-27-2008

Right. I think I suffered from the same confusion at first. Even though the SRAM chip may have a 0 ns setup, the signal still have to travel through IO buffers and PCB traces, so real-life setup is more than 0. For the similar reason, you can't run a 10 ns async SRAM at 100 MHz. However, for _synchonous_ sram it's a different story.