FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5961 Discussions

Cyclone 10 GX dev kit, which signal can I use to reset a NIOS?

Oliver_I_Sedlacek
New Contributor III
1,382 Views

I've had a look at the Cyclone 10 GX dev kit user manual and schematics but it's not clear if the board provides a signal to the C10 that will drive the NIOS platform reset input correctly. Any suggestions?

I suppose I could code up a pulse generator that runs after configuration but I was hoping for something official.

Edit - found pin AC12 has a likely sounding assignment of fpga_resetn which seems to come from a MAX10. Any clues as to what the MAX10 does with it?

Labels (1)
0 Kudos
12 Replies
FvM
Valued Contributor III
1,360 Views
Hi,
you find a brief description in user manual. Check S13 function.
0 Kudos
Oliver_I_Sedlacek
New Contributor III
1,335 Views

I found that, but that's a manual reset. How to I give my NIOS a post configuration automatic 'power on' style reset?

0 Kudos
wwanalim_intel
Employee
1,291 Views

Hi,


Thank you for reaching us.


You can enable Include cpu_resetrequest, and use a PIO IP as input into cpu_resetrequest.



Or, with the connection below made, use the debug module to reset the core only.

If the same signal is connected to other IP's reset, you can extend to full system reset.


 

You also can refer below link about this.

https://www.intel.com/content/www/us/en/docs/programmable/683836/current/reset-and-debug-signals.html


Regards,



0 Kudos
wwanalim_intel
Employee
1,287 Views

 

I am sorry for the picture above. Below I reattached the picture.

You can enable Include cpu_resetrequest, and use a PIO IP as input into cpu_resetrequest.

 

n2processor.png

Or, with the connection below made, use the debug module to reset the core only.

If the same signal is connected to other IP's reset, you can extend to full system reset.

 

interconnect.png

0 Kudos
Oliver_I_Sedlacek
New Contributor III
1,268 Views

This seems to be a way to add more reset (sink) inputs. I'm looking for a reset source to drive the reset input after FPGA configuration.

0 Kudos
wwanalim_intel
Employee
1,236 Views

I would suggest for you to connect a PIO IP to another push-button and feed it into the cpu_resetrequest.


0 Kudos
Oliver_I_Sedlacek
New Contributor III
1,188 Views

That's not what I'm after. A manual reset isn't an alternative to a configuration completion reset.

BTW it's taken me an hour to get to the point of replying to this thread because the forum software is so flaky it wouldn't put up this box for me to reply. I've tried several browsers and several login in cycles. For a billion dollar corporation this is very, very poor.

0 Kudos
wwanalim_intel
Employee
1,146 Views

It is unfortunate from our side that our suggestion is different from what you prefer. Can you elaborate more about the manual reset? We quite confused on that part.


0 Kudos
wwanalim_intel
Employee
1,075 Views

Hi,


Since you cannot replied to this thread, lets continue on the other thread that I already replied.

https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/Debugger-wont-connect-to-NIOS-II-hello-world-on-Cyclone-GX/m-p/1540301#M52293


Thank you.

Regards,



0 Kudos
wwanalim_intel
Employee
1,012 Views

Hi,


Do you have any updates to share about this issue?


0 Kudos
wwanalim_intel
Employee
938 Views

I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



0 Kudos
Kenny_Tan
Moderator
350 Views

Test

0 Kudos
Reply