Cyclone V: leakage current of Vref pins

[Zak]

Hello,

I'm designing a very compact design with a 5CEFA4 Cyclone V FPGA and a single DDR3 chip.

Following the Micron and Intel guidelines, I chose to not use VTT termination and to use only a simple resistor divider for Vref generation. I've seen that in other working designs, so I'm pretty confident all will work as expected.

To effectively choose the divider resistance value I need to know the max leakage current of Vref pin of the FPGA...anyone knows where I can find it?

On the Cyclone V Datasheet I see only the I/O pins leakage current, which is quite high, +-30uA, compared to the +-1uA of the DDR3 chip.

[Rahul_S_Intel1]

Hi ,

The maximum leakage current for the IO pins , is 30uA,

Page no: 13

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf

The above value is the characterized value from Intel FPGA .

[Zak]

Hi,

so you're telling me thah Vref pins are considered as I/O pins?

I thought they're special pins with different characteristics.

[Rahul_S_Intel1]

Hi Zak,

Kindly find the KDB for your reference, as I mentioned the leakage is only characterized for the IO, as per me the same can be considered for VREF . Kindly find the KDB for your reference.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd11122003_7976.html?wapkw=vref%20leakage