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DE1-SoC SDRAM Timing Parameters For QSYS

Altera_Forum
Honored Contributor I
957 Views

Is there a definitive source for the timing parameters to enter into QSYS for the DDR3 SDRAM on the HPS? 

 

Regards, 

Tony.
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3 Replies
Altera_Forum
Honored Contributor I
112 Views

Hi, Tony, actually, DDR3 is controlled by HPS, no need for DDR3 into QSYS, anyway, for SDRAM timing parameters, please refer to the pdf file below from your CD. 

\Datasheet\DDR3  

SDRAM\43TR16256A-85120AL(ISSI).pdf
Altera_Forum
Honored Contributor I
112 Views

That makes sense. Thanks Stewart.

Altera_Forum
Honored Contributor I
112 Views

No problem. To be frank, I like DE1-SoC device, powerful, high cost-effective, so, happy to help a little. :)

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