FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

DpX4 Simulation

Elad0708
Employee
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I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this design and it seems that the pll doesn't lock and no ref_clock or sys_clock is driven at the pll outputs. I will appricate If I can get help on this subject. 

The device is Aglilex-7. 

 

Best Regards,

Elad Rotem 

 

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Farabi
Employee
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Hello,


We will look into your PLL setting first.

  1. Do you have design example we can check your PLL parameters?
  2. If you reduce the output clock speed- can it lock?


possible cause PLL wont lock:

a. VCC to PLL not stable - need to capture scope shot

b. unstable refclk - need to capture scopeshot

c. PLL reset signal triggered - need to check schematic


regards,

Farabi



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Elad0708
Employee
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Hi Farabi, 

Thank you for your response. The model I have issue is simulation and not lab test. 

In simulation the pll doesn't lock or drive any clock at his outputs. 

Regards,

Elad 

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AqidAyman_Intel
Employee
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Hello,


May I know which example design that you are referring to? Can you pointed out to us?


Regards,

Aqid


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Elad0708
Employee
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DisplayPort using Agilex-7 Device. 

Elad 

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AqidAyman_Intel
Employee
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Hi Elad,


Is this from the IP simulation example itself as link below?

https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/simulation-example.html


It will be helpful if you can share the link pointing to the design that you mentioned.


Regards,

Aqid


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Elad0708
Employee
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Hi Aqid, 

The link you mention is for Arria V, Cyclone V, and Stratix V. I don't see any support for Agilex-7. Also, it only supports Modelsim. 

I created the DisplayPort IP from the Quartus and then press on 'create example design'. 

Regards,

Elad 

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ventt
Employee
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Hi Elad,


Are you following the steps outlined in Section 1.3 of the User Guide below to generate the Design Example for the DisplayPort Intel FPGA IP?


Please note that in this release, simulation is not yet supported for Agilex™ 7 F-Tile devices.


F-Tile DisplayPort Intel® FPGA IP Design Example User Guide


Thanks.

Best Regards,

Ven



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ventt
Employee
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Hi Elad,


Do you have further questions on this thread?


Thanks.

Best Regards,

Ven


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ventt
Employee
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Hi Elad,


We have not received any response from you to our previous reply. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.


After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.


Thanks.

Best Regards,

Ven


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