FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6027 Discussions

Ethernet PHY + MAC debugging

MKlee2
New Contributor I
863 Views

Background:
Not sure if this is the right place to ask, cause this topic basically covers multiple fields.
I'm working on setting up an ethernet PHY + MAC on a custom FPGA carrier board designed by our HW department. We use an Intel Cyclone V SoC FPGA, which features an ARM processor including an RGMII interface and a MAC. The MAC is connected to the a Ti PHY, which works as a RGMII to SGMII interface connecting a SFP fiber transceiver, which we want to connect to e.g. a Laptop.

So far I can communicate with the PHY using the MDIO interface. If I connect a Laptop to the setup using fiber the PHY tells me that it actually recognizes a link. My laptop aslo features a link LED und indicates that a link was established.

But, sadly that's about it, I can't manage to actually exchange data between the two systems (not even a simple ping). I also noticed that the auto-negotiation will not finish / isn't successful.

I tried setting up a fixed link speed but sadly to no avail.

As this is my first time debugging a PHY + MAC combo I was wondering if anyone has some suggestions, ideas or a good read for me? All help or ideas are appreciated as I don't really know where to look first.

0 Kudos
2 Replies
Paveetirra_Srie
Employee
819 Views

Hu Matthias,


Good day.

I don't have enough information on what type of MAC PHY that you're using. Kindly provide me the details.


Couple things that you can check on auto-negotiation issue


Make sure that both sides of the link are configured the same way.

**If one side of the link is set to auto-negotiation, make sure the other side is also set to auto-negotiation.

**If one side is set to 100/full, make sure the other side is also set to 100/full.

**Failure may happened if one side of the link has been set to 100/full, and the other side has been set to auto-negotiation

This may results in one side being 100/full, and the other side being 100/half.



Auto negotiation must be configure in one PHY mode and one MAC mode

**Auto Negotiation completed but 2 devices run at different speed. It was due to 2 SGMII PCS are configured with Auto Negotiation in MAC mode.  In SGMII AN, one PCS must be in MAC mode and the other in PHY mode


Auto Negotiation succeeded with mismatch ability advertised.

**It happened that "SGMII bridge" option was enabled in parameter setting but SGMII ENA bit of IF_MODE register was set to '0'.

**The SGMII mode does not disabled if SGMII bridge is enabled in the parameter setting. 

Hence, Auto Negotiation was done in SGMII mode instead of 1000BASE-X mode. dev_ability and partner_ability registers do not take effect in SGMII mode.


0 Kudos
Paveetirra_Srie
Employee
784 Views

We do not receive any response from you to the previous reply/answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.


0 Kudos
Reply