Ethernet access via FPGA in DE10 nano board

[Mahsheed]

Hello,

I am using DE10 nano board for my project, and I want to use its ethernet with FPGA. I planned to use TSE Ethernet IP core and link it with FPGA pins that are routed with PHY IC. Now when I try to assign those pins in my FPGA design, pin planner generates an error and says that these pins are not assignable.

Please help me resolve this issue. Thanks in advance.

[sstrell]

What is the exact error?  Screenshots of what you're seeing?

[Mahsheed]

unfortunately, I do not have the screenshot with me. But the error generated when I tried giving PIN_D17 and it says pin unassignable. Let me share the details from user manual.

Please see the attached picture. These pins from PHY IC are pre configured with HPS. But, I need to use this PHY IC with my  FPGA side, as I am not using HPS in my project. So apparently it generates error as these pins are connected with HPS. So I wanted to know if there is any mean that we can use these pins with FPGA too? Precedence here is HDMI ( it can be used with both HPS and FPGA)

[sstrell]

In Cyclone V, those are dedicated to the HPS, so unless you add the HPS IP and designate these pins as "loaner I/O", they can't be used by the FPGA.

[Mahsheed]

Add the HPS IP and designate these pins as "loaner I/O"
Can you please tell me how to do that?

[sstrell · Accepted solution]

I can't go through the whole HPS flow in a forum post.  Links:

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2.html

https://www.intel.com/content/www/us/en/content-details/649256/using-hps-loaner-i-o-in-cyclone-v-and-arria-v-socs.html

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/using-unassigned-io-as-loanio.html

[Mahsheed]

Thank you very much for sharing the knowledge with me. It really saved me

[Mahsheed]

Hello, Can you please answer my few queries as I am new to qsys and intermixing of FPGA and HPS.

1) I generated HDL file (SOC_system.v) from qsys after loaning my Pins. Do I just need to add that .v file into my quartus prime bdf file and make necessary connections and add this bdf file into my FPGA? (just like I used to do with my pure FPGA code)

2) I used a demonstration project to use QSYS, and it gives a lot of IO when I generate HDL file (SOC_system.v). Its difficult for me to handle all those IOs in my bdf file, as I only need Loan IO pins from HPS. So my concern is if I can remove those connections in HPS_0 before generating HDL file? If so, which signals can be removed safely without effecting the HPS loan functionality? 

Thanks in advance

[Mahsheed]

I just checked with CHATGPT. Please confirm if this is the correct method.

To designate pins as "loaner I/O" for the HPS (Hard Processor System) in the DE10-Nano, follow these steps using the Quartus Prime software:

Step 1: Set Up the HPS Component in Qsys (Platform Designer)

1. Open Quartus Prime and your project.
2. Go to Tools > Platform Designer (formerly Qsys).
3. Add the HPS component to your design:
   • Click on the "Library" tab.
   • Search for "HPS" and add it to your system.

Step 2: Configure HPS Pins as Loaner I/O

1. In the HPS component configuration, navigate to the "Pin Mux" tab.
2. Find the peripherals or signals that you want to reassign as FPGA I/O (loaner I/O).
3. Disable the peripheral function for these pins by setting them to Loan I/O.
4. Once designated as loaner I/O, these pins are now available for use by the FPGA.

Step 3: Generate the HDL for HPS

1. Once the HPS configuration is complete, click on "Generate HDL" in the Platform Designer.
2. This will integrate the HPS into your FPGA design and make the loaner I/O pins available for assignment in the Pin Planner.