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I have to create the sdc description for 0.00039MHz which was generated using counter logic.
FPGA_CLK is 26 MHz, from that i would like to specify the clk value in my sdc file
i am trying to give this clk using the below command:
create_generated_clock -divide_by 65536 -source [get_ports FPGA_CLK] -name Clkprescaler:Clockprescaler|divider[15] [get_registers {Clkprescaler:Clockprescaler|divider[15]}]
But it is not taken by the tool, its still showing the error as unconstrainted.
any suggestions?
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if timing analysis detects an incorrect or not implementable constraint, it adds a message to timing analysis report. It should explain why your generated clock isn't accepted.
I wonder what's the purpose of a 390 Hz clock in your design. In most cases, we'll use a clock enable in the respective master clock (26 MHz) domain instead, keeping a single synchronous clock domain.
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this value is used for some slower clk sensor rise fall detection. I need three slow clocks
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What does your base create_clock constraint look like? You can't create a generated clock if the base clock it references isn't constrained as well. The report there shows the base clock as unconstrained.
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base clk is FPGA_CLK which is already constrained.i don't know why the divider[15] is taken as the base type
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I believe that it is because you are constraining the clock to be too slow that is causing this problem. My suggestion is for you to use clock enable instead:
Example 1:
- reg [16:0] counter; reg clk_en; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin counter <= 0; clk_en <= 0; end else if (counter == 127999) begin // Divide 50 MHz to 390 Hz counter <= 0; clk_en <= 1; end else begin counter <= counter + 1; clk_en <= 0; end end. Adjust 127999 if using a different base clock frequency.
Example 2:
Use the generated clk_en to enable the logic that would typically run on the 390 Hz clock:
verilog
always @(posedge clk or negedge reset_n) begin if (!reset_n) begin slow_logic_state <= 0; end else if (clk_en) begin slow_logic_state <= next_slow_logic_state; end end
Thanks
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In my design, the slower clock is used as clock for one module, in this rising edge we are detecting the sensor input.
if we use the clk_en method how do we use this signal as clock?
Regards,
Abinaya
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A 0.00039 MHz clock translates to a period of approximately 2.56 milliseconds. This could lead to:
- Misinterpretation of timing constraints: The design tools may allocate unnecessarily large timing slacks, obscuring critical path analysis.
- Difficulties ensuring timing closure for faster clocks in the design.
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Instead of using a slow clock for your sensor detection module, you update it only when clk_en is high:
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sensor_state <= 0;
end else if (clk_en) begin
sensor_state <= sensor_input; // Sample the sensor input at 390 Hz
end
end
If you need to detect a rising edge of the sensor input, you can do:
reg sensor_prev; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin sensor_prev <= 0; end else if (clk_en) begin sensor_prev <= sensor_input; end end wire sensor_rising_edge = clk_en & sensor_input & ~sensor_prev;
This will trigger a pulse only when the sensor input rises at 390 Hz.
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Is there any further question base on above?
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Is there any further question?
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Is there any further question?

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