FPGA modules do not always load properly at power on

[Alexandre_Gonsette]

Hi all,

Board: DE10Nano (cyclone V + Ubuntu) + proprietary (incl: power, analog chains,  ADC's AD7761, ...)

Quartus version: quartus prime lite V 21.1

My system is an instrument consisting of a couple of rotation axes with actuators and encoders and a series of sensors. Encoders and sensor data are digitized (AD7761) and sent to the FPGA (GPIO). Within the FPGA, the encoders data are processed in 3 steps:

-A first module reads the ADC streams and put the results in registries. This works all the time.

-In the second step: a module counts the increments (incremental encoder) while another one interpolates between two increments.

-In the third step, both increments and interpolations are combined in order to get the angle.

Most of the time, everything is working well. After startup, if loaded properly, it will work well all the time until power off.

From time to time, either the counter or interpolation module does not load properly at power on (that's not always the same) . The corresponding input in the combine module (third step) seems to be floating (either zero or increasing continuously). If I reboot, it is working well again.

I first thought to  a timing closure problem but glitches would arise also when modules are loaded properly. In this case, that really depends on the startup.

Maybe I should move to Quartus standard edition.

Thanks for your help.

[FvM]

Hi,
the problem is unlikely related to Quartus version. More likely problem in your design, e.g. reset release not synchronized to clock, can result in incorrect counter initialization, illegal state machine states etc.

[Ash_R_Intel]

Hi,

The problem is likely to be related to startup conditions like reset. You may want to check the following link for recommendations on reset usage. Refer to the sub-sections also.

2.3.1. Use Global Reset Resources (intel.com)

Regards