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5282 Discussions

HPS LOAN IO Pins Not Outputting Expected Signals

DylanD
Novice
497 Views

Despite making changes inside Qsys in regards to switching desired unused pins to LOANIO from regular GPIO, exporting the new HPS LOAN IO signals, and generating new preloader files, I still cannot get the desired output from these pins. I'm confident in the VHDL design itself being correctly set up. When measuring the pins voltage with an Oscilloscope they are set 'high' and seem to remain unresponsive to any logic I set them too. Could their possibly be anything I'm missing? I've looked at almost every piece of documentation I could have and every community post that even remotely mentions LOAN IO but I still seem to be unable to get them working. Any help is appreciated.

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11 Replies
sstrell
Honored Contributor III
471 Views

Which device?  How are you making the connections?  What do your settings look like in the HPS parameter editor?  I think more details are needed here.

DylanD
Novice
464 Views

I agree and thanks for the comment.

 

Device: Cyclone V

 

How I am making the connections within design: 

Top level pin being targeted, this signal is mapped to one of the physical FPGA pins:

DylanD_0-1660656156918.png

The exported LOANIO20 signal within Qsys block is being mapped directly to top level pin as per documentation:

DylanD_1-1660656274151.png

The exported hps_loan_io_oe for LOANIO20 is set to a '1' to enable it being an output and i'm trying to output a '0' to the top level pin:

DylanD_2-1660656516076.png

 

The settings for my HPS parameter editor are as follows:

These NAND pins are set to Unused to allow for LOANIO accessibility per documentation

DylanD_4-1660656718414.png

LOANIO Signals within Qsys are being exported

DylanD_5-1660656888628.png

 

 

I am unsure if there is more information within QSYS or the HPS parameter editor that may be useful for me to include in order to solve this issue, please let me know!

 

 

 

sstrell
Honored Contributor III
454 Views

Your export name in Platform Designer (hps_h2f_loan_io) doesn't match your code so there's no connection there.  You should be seeing warnings about that.  Check the template in the Generate menu in Platform Designer to make sure you instantiate and connect correctly.

DylanD
Novice
451 Views

Oh yes sorry, I forgot I gave them different signal names when instantiating the Qsys block. 

This should clear things up, thats my bad for not including this in the first reply.

DylanD_0-1660669908487.png

 

EBERLAZARE_I_Intel
440 Views

Hi,


Are you still having issues?


DylanD
Novice
432 Views
sstrell
Honored Contributor III
440 Views

The mux table still shows the NAND interface bold for the pins you set as loaner I/O.  Is the NAND controller disabled?  You would get a conflict warning I would think.

DylanD
Novice
432 Views

The NAND interface is not being used, and there are no conflict warnings in that regard.

 

DylanD_0-1660672098013.png

 

These are the warnings I have, I do no think they are related to this issue but i hope im wrong.

 

DylanD_1-1660672187199.png

 

EBERLAZARE_I_Intel
315 Views

Hi,


Can you share your design, I would like to see the settings from my side.


EBERLAZARE_I_Intel
267 Views

Hi,


Any update from your side?


EBERLAZARE_I_Intel
237 Views

Hi,


Hope you have new updates, please check my previous responses.


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