How to set the most significant bit in an STD_LOGIC_VECTOR(data_width downto 0) to 1 without changing the other bits

[rgodw]

I'm trying to set the first bit in a logic vector to 1 so that the number is signed as a negative

[AnandRaj_S_Intel]

Hi Rory,

Yes, you can change a single bit in a vector without impacting other bits.

Example:

Data : in STD_LOGIC_VECTOR (15 downto 0);

x: out STD_LOGIC_VECTOR (15 downto 0);

.......

signal signBit : std_logic:='1';

......

signal sig : std_logic_vector(31 downto 0);

.......

sig(31)<=data(15);

signBit <= Data(15);

x(15)<='1';

Regards

Anand

[rgodw]

thank you so much that's really helped.😁