How to use AvalonMM-AvalonMM mode of mSGDMA

[2258432]

Hello,

I want to use mSGDMA to move data from the FPGA side to HPS DDR3. I referred to writing_to_hps_memory  and used the same design to complete the data movement process.

My data width is 32 bits, so like writing_to_hps_memory, I use the AvalonST-AvalonMM mode mSGDMA dispatcher to drive the write master to move data from the FPGA side to HPS DDR3.

AvalonST-AvalonMM dispatcher

But now my data width is 16 bits, and I want to change the mSGDMA dispatcher mode to AvalonMM-AvalonMM. I have referred to the official documentation and modified my design to be the same as the following image.

AvalonMM-AvalonMM dispatcherMy platform designer

After I finished modifying the design, I was confused about how to program on the HPS side to drive the mSGDMA dispatcher, so that it could drive the read master and write master to move data from the FPGA side to the HPS DDR3.

Can someone provide some examples or related documentation? Any help would be greatly appreciated.

Thank you in advance.

[2258432]

I have read some documents and learned that when using AvalonST-AvalonMM mSGDMA dispatcher, it is not necessary to specify the address for reading data, only the address for writing data. Currently, I am using AvalonMM-AvalonMM mSGDMA dispatcher, so I should specify the address to read data from.

In my platform designer, I found that the FIFO out port address is 0x5000, but I don't know how to specify this address on the HPS side.

[AdzimZM_Intel]

Hello,

I think the FIFO out port address is a secure memory regions for a slave. It's can be interpreted like in Platform Designer User Guide.

[2258432]

Hello Adzim,

Thanks for your reply. I think you are right. I tried not specifying the address for reading data, but only the address for writing data, and the result was that the data could be moved to HPS DDR3 normally.

However, I have another issue. When my data is 32-bit, I use AvalonST-AvalonMM mode mSGDMA dispatcher, and my write master parameter is set as shown in the following image.

I tried to change the Maximum Burst Count to 32, but when executing the program on the HPS side, mSGDMA did not write data to HPS DDR3, and HPS was unable to operate and had to restart.

When data is 16 bits, I use the AvalonMM-AvalonMM mode mSGDMA dispatcher, while the Length Width and Maximum Burst Count of the read/write master can only be set to 16 and 8. Setting other values will also result in HPS side failure to operate.

I would like to know what the Length Width parameter of the read/write master refers to? I couldn't find an explanation for this in the official documents.

[AdzimZM_Intel]

Hello,

It's may related to Maximum Transfer Length.

The length fields will specify the number of bytes to transfer per descriptor.

[2258432]

Hello,

I specified the descriptor to transfer approximately 24MB of data each time, and tried to set the mSGDMA for writing data and the mSGDMA for reading data separately.

When the data is 16 bits, the write side mSGDMA maximum burst count is set to 32, while the read side mSGDMA is set to 0. Now, it is normal to write data to HPS DDR3 and read it out to the FPGA side.

Thanks again for your help. Please close this thread.

Best regard.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.