Re: Re:Interfacing Nios II and HMC on Cyclone vGT

Aidin-P2D · ‎04-27-2023

Hi everyone,

Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write into DDR3 and used NIOS II to read back from every available address to confirm the data. it is working fine with no issues. NIOS II code running on on-chip memory.

Then we removed on-chip memory and tried running simple hello world. I should also confirm that SGDMAs removed from design to simplify the design. however, when we are trying to start the NIOS, the error message pops out saying “Connected system ID hash not found on target at expected base address.” I know when this happens , there might be something wrong with system. However, we are yet unable to find the issue.

I should say that HMC core passes the calibration margins. Please see attached. DDR3 using single 32 bit bidirectional port avl_0 and both NIOS data master and instruction master connected to it. exception and reset vectors correctly set and NIOS alongside other peripherals running at 50MHz. any help appreciated. I should also mention that, when we change the ip core to soft memory controller system works fine.

Looking forward to your valuable comments. Some pictures below

Regards,

Aidin.

KellyJialin_Goh · ‎05-01-2023

Hi,

Thank you for posting in Intel community forum and hope all is well.

Mind if I ask did you managed to programmed the correct sof successfully? Which quartus version are you using?

Would suggest on the following, check on the system.h files in BPS project to ensure system ID peripheral are listed with correct value, followed by regenerating the BSP to see if that helps.

As running the program in hardware, try to refresh the connection under 'Target Connections' tab.

You may also try checking 'Ignore mismatched system ID & timestamp' fields and run to the program to see if that helps.

Hope to hear form you soon.

Best Wishes

Kelly

Aidin-P2D · ‎05-02-2023

Hi Kelly,

Thanks for your reply. yes, I can confirm that we programmed correct .SOF. I am using Q22.1 10/25/2022 Lite edition

Reference system.h , I can also confirm that all values correctly set. refresh connection also done but no luck. when we are checking 'Ignore mismatched system ID & timestamp' fields, it shows a classic error "Downloading ELF Process failed".

please see below system ID properties. interestingly, connected system ID and timestamp not found. I don't understand why connecting Nios II instruction master to HMC, can cause this issue.

I will keep trying different combinations to see if any lucks but any advice greatly appreciated.

Regards,

Aidin.

Regards,

Aidin.

KellyJialin_Goh · ‎05-03-2023

Hi,

You could check out this link that might be related and helps clarify your doubts: https://www.intel.com/content/www/us/en/support/programmable/articles/000075320.html

Hope to hear on your feedback.

Thank you.

Regards,

Kelly

Aidin-P2D · ‎05-03-2023

Hi Kelly,

Thanks for your message. I am afraid that didn't work either. do you have more information on how to close DDR3 timing ? do you think this could be the cause of problem? on timing analysis , I can see some warning indicating the timing closure was not achieved.

if you need, I can share more info. This issue is very critical for us and fixing this will save us significant time/cost in project. Thanks for your help again.

Regards,

Aidin.

Aidin-P2D · ‎05-03-2023

if it helps, I am happy to share our design through secure connection for review of course if possible.

Thanks again,

Aidin.

KellyJialin_Goh · ‎05-04-2023

Hi,

The lowest supported frequency for DDR3 is 303MHz, could you try to set to 333MHz in the DDR3RAM for timing closure and see if it works on your end. I speculate that there is some kind of a PLL clock phase time rounding issue.

If not, could you try the workaround as below:

1) Using a text editor open the .qsys file, find the line :

and change it to match the FPGA part speed grade : in this case 8

Save the .qsys file.

2) In Quartus : Tools -> QSYS.

Open the .qsys file and click "Generate HDL"

3) Recompile project

Hope this helps.

Thank you.

Regards,

Kelly

KellyJialin_Goh · ‎05-07-2023

Hi,

Any updates from you end whether the workaround provided is useful?

Thank you.

Regards,

Kelly

Aidin-P2D · ‎05-09-2023

Hi Kelly,

I managed to test your suggested workaround and we could get the timing closures by reducing the frequency to 320Mhz and changing speed grade to 8. however, the problem is still there and Nios is not functioning when connecting Nios instruction master to HMC. we did implement on chip memory and nios vectors set to that memory. on BSP editor -linker script we selected .text to be onchip memory and the rest to be fpga_sdram which is HMC. system works fine with no issues. Array of 400MB defined and filled with data and verified. so the question remains why Nios system is unable to boot up/function when instruction master connected to HMC. it appears that connection brings the whole system down. any thoughts ?

thanks and regards,

Aidin.

Aidin-P2D · ‎05-07-2023

Hi Kelly,

Thanks for message and workaround and the follow up. our office is closed due to coronation in the UK and I have no access to system yet. I will get back first thing in Tuesday morning to give these try. again, truly appreciate and I will let you know results asap.

Regards,

Aidin.

KellyJialin_Goh · ‎05-09-2023

Hi Aidin,

Unfortunately, I just check the user manual that the HMC IP does not support Cyclone V GT device that you are using

with the link(Chapter 1.3 Device Family Support) here:https://www.intel.com/content/www/us/en/docs/programmable/683854/16-0/introduction.html

and that is why it cannot go through NIOS II for boot up.

Hope this clarify your doubts.

Thank you.

Regards,

Kelly

KellyJialin_Goh · ‎05-09-2023

Hi,

I have here a screenshot from the manual on the supported device family for the HMC IP:

and it does not support Cyclone V devices that's why you are seeing errors on the booting.

Thank you.

Regards,

Kelly

KellyJialin_Goh · ‎05-11-2023

Hi,

Any updates from you end whether the feedback provided is useful?

Thank you.

Regards,

Kelly

KellyJialin_Goh · ‎05-14-2023

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Thank you.

Regards,

Kelly Jialin, GOH

Aidin-P2D · ‎05-15-2023

Hi Kelly,

Thanks for your follow up and apology for delay from my side. I was out of office. we are confused and surprised with the response you provided about no support on Cyclone V GT series. CV comes with two Hard Memory Controller Support (That is what data sheet says) and we even have design examples from Altera which contains HMC IP core. even Quartus doesn't complain when we instantiate the IP core and the core works fine stand alone when it is not interfaced with NIOS II.

my question is why Intel provides device with HMC design examples with HMC IP core and you are saying that is not supported? we are very confused.

Regards,

Aidin.

KellyJialin_Goh · ‎05-15-2023

Hi Aidin,

Sorry for misunderstanding your question. Got abit caught up with our discussion but as I read through your latest comment that might be the root cause of the issue: "Nios is not functioning when connecting Nios instruction master to HMC" and "Array of 400MB defined and filled with data and verified"

Unfortunately, This Nios® II processor instruction master cannot address more than a 256 MByte span of memory; consequently, providing more than 256 MBytes to run Nios® II software wastes memory resources and causes system ID not found on target at expected base address.

I hope this answers your doubts and sorry for the confusion caused.

Thank you.

Regards,

Kelly

Aidin-P2D · ‎05-15-2023

Hi Kelly,

Thanks for information. Last week when I tried compiling the system and it wasn't working, I used Q13.1 will previous version of NIOS and it was giving me a warning that Nios instruction master can only support up to 28 bit which is exactly what you are confirming. However, now we are using Nios Gen2 and from data sheet , it must support 32 bit instruction set? am I missing a point? please see attached from Nios II Processor reference guide version 2020.10.22

based on this statement it should support 32 bit instruction set. we connected the same memory bank using soft-core and Nios II was working fine . only HMC is giving us this issue.

Regards,

Aidin.

KellyJialin_Goh · ‎05-15-2023

Hi,

You may check out the latest update on the NIOS II processer not able to address memory larger than 256Mb as you stated 400Mb data is verified : https://www.intel.com/content/www/us/en/docs/programmable/683689/current/understand-the-instruction-master-address.html

Do check out on the reference guide of External Memory Interface Volume3 (Chapter 3 on the functional description of HMC) for key points that you may have missed: https://www.intel.com/programmable/technical-pdfs/683841.pdf

Thanks.

Best,

Kelly

Aidin-P2D · ‎05-15-2023

Thanks Kelly.

will reduce HMC memory size and give it a try. I will keep you posted.

Regards,

Aidin.

KellyJialin_Goh · ‎05-17-2023

Hi,

Seems like the issue lies in the memory larger than 256Mb and causes the DDR3 unable to pass through HMC but able to go through Soft Memory Controller.

I will attach the screenshot on the CV GT user guide on the DDR HMC information for your reference: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf

Thank you.

Regards,

Kelly

Aidin-P2D · ‎05-17-2023

Thanks Kelly,

something is not adding up here . data sheet says 256MB however, Nios and Platform designer see the memory size of 512MB? could this be a problem? see below from platform designer?

Thanks

Aidin.