Issue with Altera MAX10 FPGA Development Kit and "MAX10 JTAG Secure Unlock" Example

[VecFPGA]

Dears,

I am writing to request assistance regarding an issue I am encountering with the Altera MAX10 FPGA Development Kit. Specifically, I am working on implementing the example project "MAX10 JTAG Secure Unlock" using the reference design from the "an556-ref-design" project.

After successfully downloading the project to the FPGA, I initiated the JTAG lock procedure as described. However, I am experiencing the following issues:

1. When I attempt to erase the FPGA, I receive the following error:

   • Error (209012): Operation failed

2. When I try to reprogram the FPGA, the following message appears:

   • Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are ...

Additionally, I have verified that the CONF_DONE pin remains high at all times.

I would also like to ask about the behavior of the JTAG interface. I instantiated the WYSIWYG atom primitive, which, according to my understanding, should disable the external JTAG interface. However, the "Auto Detect" click continues to works, and I am still able to scan the JTAG chain.
Could you clarify why this is the case?

I would appreciate your guidance on how to resolve these issues, as I am currently unable to erase or reprogram the FPGA.

Thank you in advance for your support.

[NurAiman_M_Intel]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

 Thank you for your understanding.

[NurAiman_M_Intel]

Hi,

Have you checked that it is being loaded with an encrypted configuration file? Tamper protection mode prevents the FPGA from being loaded with an unencrypted configuration file. When you enable this mode, the FPGA can only be loaded with a configuration that has been encrypted with your key. Unencrypted configurations and configurations encrypted with the wrong key result in a configuration failure.

Also, before programming the non-volatile key into the devices, ensure that you can successfully configure the FPGA with an unencrypted configuration file.

Regards,

AIman

[VecFPGA]

Hello, I thank you for your response.

Having no awareness of what I was doing, I think several mistakes were made on my part including :

• Instantiating the JTAG WYSIWYG atom primitive in the project to always leave it enabled by mistake.
• Place the file in my Intel Quartus Prime project directory, quartus.ini file with this setting: PGM_ENABLE_MAX10_JTAG_SECURITY=ON
  https://www.intel.com/content/www/us/en/support/programmable/articles/000074361.html.
• Do not implement any logic to perform JTAG unlock .

That's why I think now my development board is locked and there is no way to restore.

Best regards

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you