MAXII CPLD VGA CONTROLLER QUESTIONS

[Armando1989]

Hi there!

Im doing some experiment with vga under epm570t100 for 640x480 vga controller, apparently all is quite functional per results on vga screen, however i would like any comments from your expert experience... :D. Design and simulation files attached for your reference or use.

My first approach is interfacing controller with 16kx32 sram and shift each 16 bits in memory as individual pixels (black or white).

1-When interface either 16/8bit data bus i find horizontal frame barely can fit the bits(pixels), on my design, last shifted pixel at the rising edge of 25MHz clock_enable signal is just at the end of horixontal line, it is on the falling edge of the video active region... almost a glitch

Per screen results when playing with first/last pixel with external switch on data bus, it appears to eat those pixels well... (3 pixels on 1920 screen resolution equivalent to 1 pixel on 640):

Is this behavior to be expected?, maybe some designs extend a little the horizontal active region to fit pixels?

2-I find 2 port srams quite attractive for this application, since can write and read independently, u can see here an example of 16bits x32k one.

The question is... if two cheaper one port sram is to be used, have u any experience how to manage ping-pong buffering between 2 single port stams like this one?

Ie: using vsync or video enable signal to command a switch between 2 rams, one being filled the other being read.... Have u any experience on this one?

Thanks in advance!

Some extra photos for fun :D:

All 16bits "on"

3/4 bits off

all off

alternated

Board

[Wincent_Altera · Accepted solution]

Hi ,

Good try for your project.

Question 1

The behavior you're seeing can be expected when dealing with precise timing in video signal processing. To address this, consider extending the horizontal active region slightly, adding timing margins, and thoroughly testing your design. This will help ensure that all pixels are displayed correctly without glitches.

Question 2

I never try the same implementation in MaxII before, but I can lay down some of tips for you to move forward.

Using two single-port SRAMs in a ping-pong buffering scheme is a practical approach to achieve the effect of dual-port memory, especially in video processing applications where simultaneous read and write operations are necessary. Here’s a detailed explanation of how to manage ping-pong buffering between two single-port SRAMs.The basic concept involves using two SRAMs alternately: while one SRAM is being written to, the other is being read from. This alternation is controlled by a synchronization signal such as VSYNC or a video enable signal. The VSYNC or video enable signal will be used to switch between the two SRAMs, typically at the end of each frame or a predefined interval. Additionally, control logic is required to manage the read and write operations to the SRAMs.

To implement ping-pong buffering, you start by initializing the buffers. Set Buffer A as the initial write buffer and Buffer B as the initial read buffer. During the operation, while writing to Buffer A, you read from Buffer B, and vice versa. When the VSYNC or video enable signal is triggered, the roles of the buffers are switched: Buffer A becomes the read buffer, and Buffer B becomes the write buffet

Other related information about MaxII you may refer to

https://www.intel.com/content/www/us/en/design-example/714494/intel-max-10-fpga-basic-vga-display-controller-design-example.html

https://www.intel.com/content/www/us/en/content-details/654643/an-428-max-ii-cpld-design-guideline.html

Hope that able to help you move forward.

Regards,

Wincent

[Armando1989]

Hi Wincent!

Thanks for your kind reply

1. Yep, if i notice any issue on monitors, i would contract just a little porch region so extend video enable region. So far seems this one is working ok with current setup.
2. For sram thing... im not sure if is worth using some 4 latches between data/address bus on cpu/cpld and flip output enable based on wheter is reading or writing memory based ie: on vsync.... or Using 2 address and 2 data busses and alternate reading between them on cpld again based on vsync, the actual write address bus being used by cpu set cpld as high z while reading the other with cpld... Major pain for me is this multiplexing stuff. 

I guess i would go first for expensive solution double port sram :D, im little worried about bus conflict issues to be honest.

BR

[Armando1989]

Hi Wincent!

Added one more module to multiplex between SRAMS, i guess is something as you suggested... if not, let me know

Thanks in advance!

module memory_mux #(

parameter ADDRESS_BUS_WIDE,

parameter DATA_BUS_WIDE

)

(

input clk,

input reset,

input wire vsync,

input wire[ADDRESS_BUS_WIDE-1:0]INTERNAL_ADDRESS_BUS, 

input wire[DATA_BUS_WIDE-1:0]MEMORY_A_DATA_BUS,  

input wire[DATA_BUS_WIDE-1:0]MEMORY_B_DATA_BUS,

output wire[DATA_BUS_WIDE-1:0]INTERNAL_DATA_BUS,

output wire[ADDRESS_BUS_WIDE-1:0]MEMORY_A_ADDRESS_BUS, 

output wire[ADDRESS_BUS_WIDE-1:0]MEMORY_B_ADDRESS_BUS   

);

reg swap;             //SWITCH CONTROL

always @(negedge vsync)begin                                           //VSYNC FALLING EDGE WILL DIRECT CHANGE S-RAM

  if(reset)begin

       swap<=0;                                     //INITIALLY CPLD WILL READ SRAM-A AND CPU WILL WRITE SRAM-B

  end

    else

     swap<=~swap;

end

assign MEMORY_B_ADDRESS_BUS=!swap?15'bzzzzzzzzzzzzzzz:INTERNAL_ADDRESS_BUS;      //CPLD DRIVES SRAM-A ADDRESS BUS, CPLD FLOATS SRAM-B ADDRESS BUS

assign MEMORY_A_ADDRESS_BUS=swap?15'bzzzzzzzzzzzzzzz:INTERNAL_ADDRESS_BUS;          //CPLD DRIVES SRAM-B ADDRESS BUS, CPLD FLOATS SRAM-A ADDRESS BUS

assign INTERNAL_DATA_BUS=swap?MEMORY_B_DATA_BUS:MEMORY_A_DATA_BUS;              //SWITCH BETWEEN DATA PORTS

endmodule

So result is ping-pon both address buses:

Processor must know at init it should direct SRAM-B and float SRAM-A port, just the oposite cpld.... I set positive vsync as aux signal for cpu. With all of this thw whole 100 pins are used on max2 device.

Just tested with ports connected apears fine... Next would be construction of pcb and interface with some uc such as smt32...

BR

[Wincent_Altera]

Hi,

Processor must know at init it should direct SRAM-B and float SRAM-A port, just the oposite cpld.... I set positive vsync as aux signal for cpu. With all of this thw whole 100 pins are used on max2 device.

Just tested with ports connected apears fine... 

>> means everything work fine for now ? glad that you make it work,

Next would be construction of pcb and interface with some uc such as smt32...

>> you may file a new forum loop if you facing any problem to implement it . We will try out best to help out.

Do you still have any problem on VGA controller ? I would like to have your permission to close this forum support loop.

Regards,

Wincent

[Wincent_Altera]

Hi,

Just double confirm, do you have any further question on the MaxII VGA controller ?

Regards,

Wincent

[Armando1989]

Hi
So far i guess is just fine, thanks!

[Armando1989]

Hi

Ive noticed by connectio oscilloscope and logic analyzer, that address lines are plage of glitches. Both bus A and B suffers, and im worried it might be the conditional  assignements on memory_mux module.

Do u have any view on this?

Thanks

BR

[Wincent_Altera]

Hi,

Glad that my suggestion is able to help you to move forward.

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

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Regards,

Wincent

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