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Hello!
I am following https://ofs.github.io/ofs-2024.2-1/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/ to set up OneAPI for the Agilex 7 I-Series Development Kit (2x R-Tile, 1x F-Tile).
At step 2.5.1 Compile Initialization Bitstreams the command
./build-default-binaries.sh -b ofs_iseries-dk
failed with the output in the attached file.
Regarding the Verilog error, I found this https://www.intel.in/content/www/in/en/programmable/quartushelp/22.1/index.htm#msgs/msgs/evrfx2_veri_opposite_direction.htm. Is there actually an error in ofs_plat_prim_burstcount1_mapping_gearbox.sv or am I doing something wrong?
All tools should be the versions mentioned in the OneAPI ASP Getting Started Guide but the host OS is Ubuntu 24.04.
I would appreciate some help. Thanks!
Felix
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Hi @gustifix2,
Thank you for posting in Intel community forum and hope all is well.
Noted on the issues faced with the details explanation, please do provide us some time to check issues mention.
Will get back to you as soon as possible.
Appreciate the patients.
Best Wishes
BB
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Hi @gustifix2,
Appreciate the patients, after some discussion and alignment it seems that the oneAPI OFS design example required specific RAM configuration which is 2x8GB, hence after some OFS configuration setup with the right RAM configuration setting, the oneAPI kernel compilation would be successfully.
Hope that clarify, please do let us know if there is further doubts.
Best Wishes
BB
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Hi @gustifix2,
Greetings, just checking in to see if there is any further doubts in regards to this matter.
Hope your doubts have been clarified.
Best Wishes
BB
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Hi @BoonBengT_Intel ,
Thank you for the response! I haven't had time to try your solution yet, but when I get to it, I will post here to let you know if it worked.
Best regards
Felix
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Hi @gustifix2,
Sure thanks for the updates, hence while waiting for future updates, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
Thank you for the questions and as always pleasure having you here.
Best Wishes
BB
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Hi @BoonBengT_Intel ,
Could you point me to some documentation for what exactly should be changed? I assume I have to change the memory configuration of the FIM, similar to 4.7 Modify the Memory Sub-system. I tried removing the 2 DDR4 interfaces with location "North I/O Row" in the picture below:
I assume the "North I/O Row" is connected to the two DIMM slots and "South I/O Row" to the 2x8GB soldered to the board based on this picture:
However, with just two "south" interfaces and after removing unused signals in the "Interface Requirements" window, I get a compilation error in build_top.sh script about the fitter not being able to place pins. It looks like I also have to adjust the pin constraints and remove the now unused pins. However, I'm not sure if this is even the right approach to change the RAM configuration to 2x8GB, so I wanted to ask here again first.
Also, I will be on vacation for two weeks and continue to work on this afterwards.
Thanks and best wishes!
Felix
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Hi @BoonBengT_Intel,
We are looking into the following up enquiries and will get back to you as soon as possible.
Please do expect some delay due to the holiday season.
Thank you for the patients
Best Wishes
BB
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Hi @gustifix2,
Thank you for waiting and the patients.
After discussing this internally with our IP team, since the error are mentioning the fitter problem and we have unused pin. Hence we should remove them with the correct pin constraint.
It should work per the example design which requires 2x8gb external memory.
Hope that clarify.
Best Wishes
BB

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