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Qsys-based example design for a Cyclone V GX Dev Board

Honored Contributor II



I'm struggling to get DDR3 accesses working on the dev board and am wondering if anyone has a Qsys-based design working yet. Basically, I get an error when I attempt to download my .elf and receive the following message when I attempt to control the NIOS using System Console: 


error: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset 

while executing 


The EMIF toolkit seems to indicate that it can access the DDR3 ok and the provided example design (DDR3A) indicates a pass. The DDR3A example design appears to be pretty simplistic in that it doesn't use bursting (from what I can see in SignalTap). I initially thought that perhaps the DDR3 timing parameters were wrong. When I 'grep' through files in the example design, several files contain parameters (of which some are different) and none of them correspond to the speed grade of the DDR3 on the actual board. That said, I've tried a bunch of different combinations (Micron datasheet, parameters provided with kit) with no success. 


Any help appreciated. 

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