Signaltap waiting for clock on PCIe example design

[binupr]

Hi there,

I am running PCIe example design on AGF027 development kit. I am running Gen4, 1x16 Endpoint reference design. Using Signal tap to check basic functionality. I ran through the process as mentioned in User Guide, generated sof from Quartus. Able to program the sof onto the board. But when I run signaltap, I get "waiting for clock". The clock I am using for signal tap is coreckout_hip which is an output of the PCIe Streaming IP and intended for use in application logic. Have ran previous boards AGF014 using same example design and clock but have not seen this issue.

Still looking through board to see if clock is coming all the way. But I also came across this old article https://community.intel.com/t5/Programmable-Devices/waiting-for-clock/td-p/74580 refering to using Post fitting clock signal. Funny thing is I cannot even see this clock in post-fitting. Then I opened Netlist post fitting view and I do see input to System PLL but no output. Has any body come across any of these issues? I am using Quartus 23.4?

Thanks

BPR

[sstrell]

Can you temporarily try some other sampling clock just to make sure the issue is with this clock?  You'll have to recompile, but it will help you narrow down the problem.

[binupr]

Yes I have already tried those experiments. I ran a counter with General Purpose FPGA clock and that is showing as free-running/can trigger a signal tap instance.

[binupr]

In one of the experiments, I tried bringing out the lock from System PLL to an LED and I cannot see it getting asserted. So I do think the System PLL is not locking to these reference clocks. Surely I can think it is a board issue but these boards are from Intel and I see same behaviour on 2 such boards.

My suspicion is whether this is a bug in Quartus 23.4. Something similar to https://www.intel.com/content/www/us/en/support/programmable/articles/000092708.html?wapkw=System%20PLL%20IP.

[wchiah]

Hi Binu,

Which Tile you are using for this ? F-tile or P-tile ?

Can you please sent the printscreen error between post-fitting signals and pre-synthesis signals ?

SignalTap showing "waiting for clock" typically means that SignalTap is not detecting the clock signal for the specified clock domain. This could happen due to several reasons:

1. Clock Selection: Ensure that you have selected the correct clock for the PCIe Avalon Streaming example. It should be the same clock that drives your Avalon ST interfaces.
2. Connection: Verify that the clock signal is correctly connected to the SignalTap instance. Double-check the SignalTap setup to ensure the correct clock is selected.
3. Timing: If the clock is gated or not running during the capture, SignalTap may not detect it. Ensure that the clock is active when you start capturing.
4. Clock Domain Crossing: If there are asynchronous crossings in your design, ensure that the clock domain for SignalTap is correctly set up to capture signals crossing those domains.
5. Reset: Ensure that any required resets are correctly applied and released to allow the design to start operating.

Maybe you can try to generate a new example design, please ensure that you select the "target devkit" so that all the pin can be assign properly.

Regards,

Wincent_Intel

[binupr]

Hi Wincent,

Thank you for your response.

As I am targeting AGF027 FPGA board, the design uses F-tile.

Please see my comments marked [Binu].

1. Clock Selection: Ensure that you have selected the correct clock for the PCIe Avalon Streaming example. It should be the same clock that drives your Avalon ST interfaces.[Binu] Yes it is the correct clock. It is the coreclkout_hip from the PCIe Avalon streaming IP. Have used this same clock for a P-tile based example design in past.
2. Connection: Verify that the clock signal is correctly connected to the SignalTap instance. Double-check the SignalTap setup to ensure the correct clock is selected.[Binu] As far as I can see, there is no red mark around this clock setup in SignalTap. I am using pre-synthesis selection.
3. Timing: If the clock is gated or not running during the capture, SignalTap may not detect it. Ensure that the clock is active when you start capturing. [Binu] This is something which I am still checking from our hardware setup.
4. Clock Domain Crossing: If there are asynchronous crossings in your design, ensure that the clock domain for SignalTap is correctly set up to capture signals crossing those domains. [Binu] This is not my custom design. It is Altera's PCIe reference design out of the box.
5. Reset: Ensure that any required resets are correctly applied and released to allow the design to start operating. [Binu] This is a good point. It crossed my mind too. Another one to check from hardware setup.

Regards

Binu

[wchiah]

Hi Binu,

Maybe you can check the point no5.
Do you try to generate an example design by selecting the "target devkit" via IP catalog ?
If not, I do suggest you to try so.

Regards,

Wincent_Intel

[binupr · Accepted solution]

Hi Wincent,

Finally narrowed down the issue. 

Issue was that the Switch selection option for PCIe reference clock mentioned in Intel/Altera AGF027 dev kit user guide was incorrect and this led to the clock buffer put in wrong input mode. 

Below is screenshot from User Guide.

Switch 4.3 should be set to OFF to receive local clock. As you can see the documentation suggests setting to be ON to receive local clock.

Could you please feed this back to the corresponding documentation team within Intel/Altera to get this updated? 

Thanks

Binu

[wchiah]

Hi Binu,

Glad that you find the solution, also thanks for sharing with me.
I will feedback to the related team to cross check on this and proceed to update.

Regards,

Wincent_Intel

[wchiah]

Hi Binu

As the solution is found, I will proceed to close this thread

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.