Stratix V PCIe CvP not working

[Petkov_Alex]

Hello! I have a board with Stratix V GT, PCIe HIP works good at Gen3 x8. I want to use it as CvP.

So, i downloaded reference design, made chnages in assignment editor and compiled project. My setting are the same as in PCIe user guide. Gen 1, x1. Other needable setting were made too.
Next I converted .sof file to periph.jic and core.rbf. Loaded jic to mt25ql512. Rebooted board, inserted into PC and got nothing.

I then made from this project .sof file without CvP and pcie works.

Additionally my board pin nperst L0 for pcie not connected to pcie... This pin connected to other pin. But as for user guide for pcie gen1 i have exact pin because used hard teset. For gen2 and gen3 used sort reset.

My project without cvp and gen1 i set in assignment editor pin nperst set weak pull up resistor.
I tried to set cvp with gen2, but megawizard shows me error, that gen2 and gen3 does not support cvp, but in user guide in table there mentioned that stratix v cvp support gen1 and gen2.

So i have several questions:
1.Does stratix v gt support cvp with gen2?
2.How can i set nperst pin assignment for pcie, that quartus put it in periph.jic image. Because as i right understanded KB, in periph image only hard pcie, my assignment with pull up resistor for pin not used... And thats why my periph image not start(pcie).

Need any help! Thanks!

P.S. Tried Quartus 18.1, 20.1.

[wchiah]

Hi,

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best regards,

Wei Chuan

[wchiah]

Hi,

1.Does stratix v gt support cvp with gen2?

• CvP is available for Gen1 and Gen2 configurations. Detail you may refer to Userguide at link below under Section10-2, Page 190/286
• https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset01/stratix-v-hard-ip-for-pcie.pdf

2.How can i set nperst pin assignment for pcie, that quartus put it in periph.jic image. Because as i right understanded KB, in periph image only hard pcie, my assignment with pull up resistor for pin not used... And thats why my periph image not start(pcie).

• You can refer to KnowledgeBase "How should I use the four dedicated PCI Express nPERST* pins on Stratix V devices?"
  
• https://www.intel.sg/content/www/xa/en/support/programmable/articles/000074772.html

Let me know if this is helpful.

Regards,

Wincent_Intel

[Petkov_Alex]

As for the first question and your answer user guide Stratix V support cvp on gen 2, but platform designer does not in Q 18.1 and 20.1. I will attach screenshot

 

[wchiah]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel

[Petkov_Alex]

I replied here and at support ticket.

[wchiah]

Hi,

The ticket is still open, Please allow me to have sometime investigate on this issue.

Get back to you soon as possible.

Regards,

Wincent_Intel

[wchiah · Accepted solution]

Hi,

Thanks for the additional information and printscreen, Apologize for missing some important information.

I do a deep check for Stratix V CvP gen2 procedure.

Indeed Stratix V does support CvP at Gen2, due to a published errata, customers must order specific product variants with fixed silicon.

Please see errata, PCIe Gen2 Link Training Error When Using Hard Reset Controller. As CvP must use the hard reset controller, then this errata applies.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_stratixv.pdf#page=2

The good news is that a fix part is available, your customer is reported as using:

5SGSED8N2F45I2L

But they must order parts with the full part number:

5SGSED8N2F45I2LCV

The *CV indicates fixed PCIe Gen2 silicon Hard Reset Controller.

Without fixed silicon, only Gen1 is supported in Stratix V.

Hope this clarified,

Regards,

Wincent_Intel

[wchiah]

*** repost due to typo at recent sent

Hi,

Thanks for the additional information and printscreen, Apologize for missing some important information.

I do a deep check for Stratix V CvP gen2 procedure.

Indeed Stratix V does support CvP at Gen2, due to a published errata, customers must order specific product variants with fixed silicon.

Please see errata, PCIe Gen2 Link Training Error When Using Hard Reset Controller. As CvP must use the hard reset controller, then this errata applies.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/es/es_stratixv.pdf#page=2

The good news is that a fix part is available, Please refer to KDB below

https://www.intel.com/content/www/us/en/secure/support/programmable/articles/000083884.html

The *CV indicates fixed PCIe Gen2 silicon Hard Reset Controller.

Without fixed silicon, only Gen1 is supported in Stratix V.

Hope this clarified,

Regards,

Wincent_Intel

[Petkov_Alex]

For the first question thanks a lot for excellent explain!
For the second question, about pesrtn pin. Maybe i explained not good. I have board, where pin perstn from pcie is not, where expected for hard reset. So pin, where actually comes perstn is iodiff pin, and perstn pin expected for hard reset not connected anywhere (
If I disabled cvp and make assignment gor pin that comes to hard reset "weak pullup resistor", and program.sof file or jic files. My pcie works good.
But if i enable cvp, and split sof file to periph.jic and core.rbf files it seems that assignment with "weak pullup resistor" not used in periph.jic and putted by quartus to core.rbf file.
If i try to use my pin where developer of board putted nperst from pcie slot, fitter goes to error because hard ip expect other pin.
I hope I explained better this time.
Hope any help.

[wchiah]

Hi ,

Thanks for your clear explanation, To be honest I am not familiar with nperst pin as I never did it before.

Is there any error happen for the setup ?

If you are confused about the pin and what it does, you may refer to the user guide Under Table 6-7 page 119/286

It might have some idea for you to setup the whole nperst pin

Let me know if you still need any of our help.

Regards,

Wincent_Intel

[Petkov_Alex]

I read this document. So can i some how put my assignment for gpio pins put into periph.jic, not in core.rbf file.

[Petkov_Alex]

https://www.intel.com/content/www/us/en/support/programmable/articles/000078209.html this state of KB tells, that all pin, that are not used for hard ip and reset in tri-state and Quartus II does not have a way to change it? What about actual versions of Quartus?

[wchiah]

Hi,

Can I check with you if you programming the CvP image following at step below ?

https://www.intel.com/content/www/us/en/docs/programmable/683889/current/programming-cvp-images-and-validating.html

For the CvP configuration and those pins you mention, I wish to explain them to you.

But I believe the link below shows provide a more clear information/step which can help you more.

https://www.intel.com/content/www/us/en/docs/programmable/683889/current/cvp-configuration-images.html

Let me know if any further clarification is needed.

Regards,

Wincent_Intel

[Petkov_Alex]

I understand, that cvp would not work in my board, because of bad planning board for this needs.
By thanks a lot for Your help!!!

[wchiah]

Hi Alex,

Glad that you found the way to solve this. Such nice working with you.

With that said, I will close this case from my place. This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel