Trying to update Arria 10 example project from 2017 Quartus Prime Pro to 22.3 Quartus Prime Pro

[ccusi]

I am currently responsible for getting a Terasic Arria 10 development kit up and running for my company.

I am having issues with the QIP file that conjoins multiple file paths for the Intel IP currently in the project. I believe this issue is arising since this project was originally made in an older version of Quartus.

The auto generated QIP file uses The set_global_assignment command.

set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "crc32/crc32_gen.v"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "crc32/crc32_chk.v"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "crc32/avalon_st_to_crc_if_bridge.v"]

The error I receive is as follows for all set_global_assignment commands. (there is a lot of them)

global setting for OUTPUT_IO_TIMING_NEAR_END_VMEAS is not supported. Please use this setting with pin assignments.

My understanding is this is no longer supported in Quartus Prime Pro after Version 18.1.

https://www.intel.com/content/www/us/en/support/programmable/articles/000074366.html

Is there an easy replacement for this set_global assignment command in the QIP file?

[sstrell]

.qip files get regenerated when you regenerate or update the IP.  You should just be able to use the IP update manager (File or Project menu in Quartus, I forget which right now) to update the old IP to work with the new version.  Usually when you open an old project in a newer version of the software, a yellow banner appears at the top of the project navigator to indicate that IP needs to be updated.

You shouldn't have to manually edit the .qip.

[ccusi]

Thank you for replying.

I have updated all of the IP in the Upgrade Ip Components tab. I have no IPs listed as must upgrade.

I see that I have incorrectly identified where my error message is coming from. I am currently failing in the plan portion of the compilation flow of the project. My guess is the issue is in the sdc constraints file.

Most of my design experience has been in the Xilinx/Libero design platforms and I am guessing the issue would most likely be in the .sdc constraints file. I am unclear of where exactly my error could be. The constraints file is setup with an if statement rather than showing individual pin assignments. I am unsure of how this sdc file works in combination with the pin planner which shows the individual pin assignments.

"

# Function to constraint pointers
proc alt_em10g32_constraint_ptr_top {from_path from_reg to_path to_reg max_skew max_net_delay} {


if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
# Check for instances
set inst [get_registers -nowarn *${from_path}|${from_reg}\[0\]]

# Check number of instances
set inst_num [llength [query_collection -report -all $inst]]
if {$inst_num > 0} {
# Uncomment line below for debug purpose
#puts "${inst_num} ${from_path}|${from_reg} instance(s) found"
} else {
# Uncomment line below for debug purpose
#puts "No ${from_path}|${from_reg} instance found"
}

# Constraint one instance at a time to avoid set_max_skew apply to all instances
foreach_in_collection each_inst_tmp $inst {
set each_inst [get_node_info -name $each_inst_tmp]

# Get the path to instance
regexp "(.*|)(${from_reg})" $each_inst reg_path inst_name reg_name

set_max_skew -from [get_registers ${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] $max_skew

set_max_delay -from [get_registers ${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 100ns
set_min_delay -from [get_registers ${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
}

} else {
set_net_delay -from [get_pins -compatibility_mode *${from_path}|${from_reg}[*]|q] -to [get_registers *${to_path}|${to_reg}*] -max $max_net_delay


# Relax the fitter effort
set_max_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 3.2ns
set_min_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
}

}

"

If the error is not related to the sdc file I am unsure of what file the error messages are related to in the project.

[sstrell · Accepted solution]

It's not SDC.  Check the Assignment Editor and the .qsf file itself.  You can safely remove those board trace model assignments.

[SyafieqS]

May I know if there is any update from previous reply?

Also, speaking of design migration, the design example is meant by that particular version, and normally (most of time), there is extra labor needed to fix when you are migrating to latest version.

[SyafieqS]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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