Write from BRAM to 2D array in transpose manner

[Nupoor]

I have initialised single port BRAM of IP core with .coe file. BRAM is of 8x10 dimension having we_A,dout,din,addr,clk and declare a 2D array of 10x8 dimension.

I want to read from BRAM and write into the 2D array in transpose form, as the dimensions of both are different. I am using VHDL.

Below is the code. Kindly help me in transpose write in array. I am having problem in the logic inside the process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

use IEEE.NUMERIC_STD.ALL;

entity dummy_handle is
Port ( clk : in STD_LOGIC;
--test : out STD_LOGIC_VECTOR(7 DOWNTO 0);

rst : in STD_LOGIC);
end dummy_handle;

architecture Behavioral of dummy_handle is

type array2D is array (0 to 7 ) of STD_LOGIC_VECTOR (9 DOWNTO 0);
signal M: array2D;
signal addr_array : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";

signal we_A: STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal addr : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal test : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal i : integer:= 0;

COMPONENT array_print
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

begin
test <= dout;
print_array : array_print
PORT MAP (
clka => clk,
wea => we_A,
addra => addr,
dina => din,
douta => dout
);

dat_process: process(clk)

begin
if rising_edge(clk) then
if addr = "1010" then
addr <= "0000";
else
for addr_array in 0 to 7 loop
M(to_integer(unsigned(addr_array)),i) <= test(i);
addr_array <= addr_array + 1;
end loop;
addr <= addr + 1;
end if;
end if;
end process dat_process;
end Behavioral;

[KhaiChein_Y_Intel]

Hi,

You may use the template in Quartus to infer the RAM. You can open Insert Template Dialog Box by clicking Insert Template on the Edit menu with a file open in the Quartus® Prime Text Editor.

Thanks

Best regards,

KhaiY

[Nupoor]

dat_process: process(clk,addr,i,j,test)
begin
if rising_edge(clk) then



if j = 9 and addr = "1001" then
addr <= "0000";
j <= 0;
i <= 0;

else


M(to_integer(unsigned(addr_array)),j) <= test(i);
addr_array <= addr_array + 1;
i <= i + 1;

if addr_array = "111" and i = 7 then
j <= j + 1;
addr <= addr + 1;
addr_array <= "000";
end if;




end if;

end if;

end process dat_process;
end Behavioral;

I am using the above logic but it runs ok for the 0th column of the array but the rest column value up to 9 is showing undefined.

[Nupoor]

M using Xilinx ISE.

[KhaiChein_Y_Intel]

Hi,

Do you see this problem in Quartus software? If yes, could you create a QAR file and steps to reproduce the error? To create the QAR file, click on Project > Archive Project > Archive.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY