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clock gate conversion issue

ymiler
Employee
885 Views

Hi

 

My  FPGA desgin is prototype which use for ASIC RTL , 

Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock )

Additionally, the clock gate instance includes a solution for glitch clock by enabling/disabling the clock at the falling edge (using a NOT logic element) :

ymiler_0-1714576258445.png

The current synthesis & mappin are performed  by Synplify Premier tool and P & R by Quartus ( version 22.3 ) 

The clock gate solution is :

Same clock for all the FF's enabling the selection of the appropriate rate via a multiplexer (mux).

Regarding the glitch mux soultion which has 'not' logic element  - Synplify Premier create a new output clock from the PLL referred to as <clock_name>_inv_proxy and create relevant constraint for Quartus - all these worked fine without any timing issues  ,

ymiler_2-1714577667087.png

 

 

 

Now I'd like to do all the process in Quartus ( for same design )

Quartus doesn't automatically generate a new inverted clock from the PLL. Instead, it retains the 'not' logic element."

ymiler_3-1714577732682.png

this status cause to setup vilolation since the clock routing is as other logic elements routing 

 

please advice 

 

 

 

 

 

 

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13 Replies
sstrell
Honored Contributor III
862 Views

Can't you just invert the clock in the PLL output settings?

Side note: none of what you mentioned is recommended for FPGA design (latches and gated clocks), though you do mention this is for prototyping an ASIC design.

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ymiler
Employee
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There are 2 paths for same output source clock 

 

1) posedge edge ( FF's )

2) negedge edge ( for glitchless mux code )

 

If I simply invert the PLL clock, I can change the functional code

Synplify Premier didn't change the functionality by adding 1 more output clock from PLL (  specific to glitch mux code ) and removing  the 'not' gate in the "glitch mux" code 

 

 

 

 

 

 

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ShengN_Intel
Employee
820 Views

Hi,


How about adding clock inversion primitive from PLL to glitch mux which has 'not' logic element?


Thanks,

Regards,

Sheng


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ymiler
Employee
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This is an option, but I prefer to do not change the code manually.

The preferred option is for the tool to be able to solve the problem on its own

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ShengN_Intel
Employee
720 Views

Hi,


Probably this is something to be enhanced. Could you provide a minimal test case for duplicating the limitation?


Thanks,

Regards,

Sheng


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ymiler
Employee
708 Views

I'll try to generate minimal test case

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ShengN_Intel
Employee
656 Views

Sure, will wait for the minimal test case.


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ymiler
Employee
578 Views

Hi

 

For the beginning, I create a test case with minimal design:

 

PLL - > clock gate -> counter (with no inverse clock)

I have the flag : 

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON

 

Why Quartus did not convert the clock gate?

 

 

 

 

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ShengN_Intel
Employee
562 Views

Hi,

 

You need this further assignment set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK ON -entity bonsai_top

 

Report screenshot:

ShengN_Intel_0-1715872012688.png

 

 

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ymiler
Employee
556 Views

Indeed , It's working !!

Thanks 

 

Now , I added 1 more clock gate .

Meaning the output clock of CG A is connecting to CG B input clock 

( attached new archive file )

 

I have same case in my prototype RTL release 

 

In this case , Quartus didn't convert the clock gates

 

please advice

 

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ShengN_Intel
Employee
422 Views

Hi,


When you cascade CG A and CG B, it forms a gated clock tree. Latch (CPEN) is an unsupported gate in the gated clock tree. May be can use flip-flop or combinational logic for the clock gating cascading.


Thanks,

Regards,

Sheng


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ShengN_Intel
Employee
214 Views

Hi,


May I know do you have any further update or concern?


Thanks,

Regards,

Sheng


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ymiler
Employee
202 Views

Just ask to support CG cascading case in the next release 

 

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