FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

output delay

ymiler
Employee
305 Views

Hi

Here the data path values which provide by Quartus ver 22.3 from the ALM to I/O pad 

ymiler_0-1718778838956.png

I try to understand why there is so much latency in the I/O output buffer and how can I decrease it 

( the tool didnt succeed to get positive slack for my output delay constraint since I have high routing value )

 

Thanks

 

 

 

 

Labels (1)
0 Kudos
4 Replies
sstrell
Honored Contributor III
259 Views

An I/O is a physical location assignment.  If the selected I/O pin is far from the previous LAB, you'd get a result like this.

You can either choose a different I/O pin, if that's possible for your design, or try to figure out why the Fitter placed the previous logic in the path so far from the selected I/O.

You may also want to try turning off the optimize hold timing option, which intentionally adds additional routing delay to help meet hold timing requirements.

0 Kudos
ymiler
Employee
244 Views

1) How can I try turning off the optimize hold timing option? via GUI? command?

2) What is the meaning of turning off this option? I'll get holding violation? 

 

 

0 Kudos
sstrell
Honored Contributor III
219 Views
0 Kudos
ymiler
Employee
184 Views
0 Kudos
Reply