FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

virtual clock

ymiler
Employee
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Hi

 

Is there an option to define clock delay for virtual clock ?

 

Thanks 

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sstrell
Honored Contributor III
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No.  A virtual clock never enters the FPGA so it wouldn't make any sense.

For a synchronous I/O design, the delay is included in your set_input_delay or set_output_delay constraint.

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ymiler
Employee
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OK

 

So , How can I compensation the launch clock delay ?

 

Let's take my case :

 

I'd like to define output delay see the report:

ymiler_0-1718826512001.png

in this example :

My budget is 8ns - launch clock 128Mhz and latch clock 128Mhz as well ( virtual clock )

I want to define max delay of 3ns

 

but in my case :

The clock launch delay is 3.279ns 

Routing to pin is 5.779ns

Meaning : 3.279ns + 5.779ns = ~9ns  which mean there is no option to close timing ( even without the max delay constraint of 3ns ) since the routing includes launch clock delay when the virtual clock no exist at all latch clock delay 

 

I don't approach this issue in the FPGA internal logic because of the tool calculate similarly delay to launch and latch clock ( when both same frequency and sync )

But ,in my case  when launch clock is internal and latch clock is virtual there is no compensation of the clock routing delay  

 

 

 

 

 

 

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sstrell
Honored Contributor III
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This is not how set_output_delay works.  The value you choose for set_output_delay specifies the maximum or minimum external delay in order to meet the downstream device's setup or hold timing requirement.  The Fitter uses this info to set the placement of the output register appropriately.  What are your set_output_delay -max and -min constraints for this output?

They should look like:

set_output_delay -clock <downstream virtual clock> -max <maximum external delay to still be able to meet setup timing> <output port(s)>

set_output_delay -clock <downstream virtual clock> -min <minimum external delay to still be able to meet hold timing> <output port(s)>

The calculated values use the formulas: 

max: Data trace (max) – Board clock skew (min) + Tsu

min: Data trace (min) - Board clock skew (max) – Th

so it takes into account the data delay between the two devices and the skew between the clocks arriving at both devices.

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