High Speed Transceiver Demo Designs - Intel Agilex® FPGA F-Series (E-tile)

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High-Speed Transceiver Demo Designs - Intel Agilex® FPGA F-Series (E-Tile)

• For a list of Intel Agilex® FPGA I-Series (F-Tile) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Agilex-I-Series-F-Tile/ta-p/1315123 
• For a list of Intel® Stratix® 10 TX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-TX-Series/ta-p/735133 
• For a list of Intel® Stratix® 10 GX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749 
• For a list of Intel® Arria® 10 High-Speed Transceiver Demo Designs, go here:  https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Arria-10-Series/ta-p/735131 
• For a list of Intel® Stratix® V-Series (SVGX, AVGT, AVGX, and CVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-V-Series-StratixV-ArriaV-and/ta-p/735783 
• For a list of Intel® Stratix® IV-series (SIVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-IV-series-StratixIV-GX/ta-p/735787 

Index

1. Multi-Prbs Generators and Checkers
2. Script with useful procedures for use in the system console for Agilex (E-Tile)
3. Library of C-functions for E-tile transceivers using AVMM Interface
4. Superlite II V4 (no FEC)
5. 100GbE
6. Soft PRBS with/without RSFEC + Dynamic Reconfiguration Test Designs

1. Multi-Prbs Generators and Checkers

• (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths: 32-bit, 64-bit, 128-bit, and 256-bit. Includes testbench as well. 
  • multi-prbs-generators-checkers.zip

2. Script with useful procedures for use in the system console for Intel Agilex® FPGA (E-Tile)

• Updated (12/05/2020)
  • ttk_helper_s10tx.tcl  V1.13 (12/05/2020) 

3. Library of C-functions for E-tile transceivers using AVMM Interface

• Functions for configuring PMA settings, adaptation, etc. (The same as from the Stratix 10 TX page) :
  • pma_functions_etile.zip (31/10/2019)

4. Superlite II V4 (no FEC)

• (09/11/2020) Intel Agilex® FPGA SOC Kit (ES Version): Superlite II V4 Demo design using 2 times 4 lanes at 25.78125 Gbps to transport 100 Gbps of raw data.
  •  agilex_soc_Kit_superliteII_v4_etile_2x4_lanes_26Gbps_dual_qsfp.zip (20.3 B158) 

• (24/11/2020) Agilex PCIe Kit (ES Version): Superlite II V4 Demo design using 2 times 4 lanes at 25.78125 Gbps to transport 100 Gbps of raw data.
  •  agilex_pcie_Kit_superliteII_v4_etile_2x4_lanes_26gbps_dual_qsfp.zip (20.3 B158) 

• (24/11/2020) Agilex PCIe Kit (ES Version): Superlite II V4 Demo design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data.
  • agilex_pcie_Kit_superliteII_v4_etile_2x4_lanes_10gbps_dual_qsfp.zip   (20.3 B158) 

5. 100GbE

• (12/02/2021)  Agilex PCIe Kit (ES Version):  Dual 100GBase-KR/CR2 (with AN/LT) PAM4 Demo design using QSFPDD0 and QSFPDD1.
  • agilex-f-devkit-100g-dual-qsfpdd-pam4-anlt.zip (20.4 B72) 

6. Soft PRBS with/without RSFEC + Dynamic Reconfiguration Test Designs

• (19/05/2021) Agilex PCIe Kit (ES Version): 2x 4 channel NRZ/PAM4 26 Gbps soft PRBS test design. Can be dynamically reconfigured to 10.3125 Gbps.
  • Connected to QSFP-DD Modules  + Adaptation Soft IP in each PHY, + LPM + PMA configuration supports + I2C, etc.
  • agilex-pcie-kit-2x4ch-qsfpdd-adapt-sip.zip  (21.1 B169)

• Updated (15/02/2022) Agilex PCIe Kit (ES Version): 2x 4 channel NRZ 28.3 Gbps soft PRBS with RSFEC in FRACTURED mode test design that can by dynamically reconfigured to :
  • NRZ/PAM4 RSFEC Fractured (528,514) (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate)              
  • NRZ/PAM4 RSFEC Fractured (544,514) (line rate is 26.5625 Gbps from 156.25 Mhz clock (x170) or any reconfigurable rate)   
  • PAM4 KPFEC Aggregate (544,514) with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate) 
  • NRZ PMA direct mode with 4 physical lanes (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate) 
  • PAM4 PMA direct mode with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate) 
  • NEW: Reconfigure individual lanes 1-3 from RSFEC to PMA direct (line rate is (tx_clk_divider (configurable)  x refclk frequency), and PMA direct to RSFEC fractured.
  • NEW: when all lanes are in PMA direct NRZ mode: reconfigure lane 0-3 to any reconfigurable datarate (line rate is (tx_clk_divider (configurable)  x refclk frequency)
  • Connected to QSFP-DD Modules + Adaptation Soft IP in each PHY, + LPM + PMA configuration supports + I2C, etc.
  • Agilex-PCIe-Kit-2x4Ch-qsfpdd-adapt-sip-rsfec-fract-to-kpfec-aggr-pma-direct.zip (21.4 B67)