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This Intel FPGA Wiki was shut off to the public on June 28, 2019, and has since moved to the Intel Forums.
Redirects have been implemented to redirect each wiki page to its new home in the Intel FPGA Forum for the external customer experience.
To navigate to the new community FPGA Wiki pages, go to https://community.intel.com.
Or click here for a direct link to the FPGA Wiki section of the Intel Communities.
Note: Each post in the FPGA Wiki tab replicates its previous Intel FPGA Wiki page.
If you find asset links or pages on the Intel FPGA Wiki that need to be cleaned up or have any general questions or concerns, please contact ForumSupport@intel.com for any forum-related issues.
We apologize for any inconvenience caused and greatly appreciate your help informing our customers of this migration to Intel Communities.
For more complete information about compiler optimizations, see our Optimization Notice.