What steps can I follow to bring up the E-tile PAM4 PMA?

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What steps can I follow to bring up PAM4 PMA in Intel® Stratix® 10 FPGA / Intel Agilex® FPGA E-tile design?

Intel® Stratix® 10 FPGA/Intel Agilex® FPGA E-tile PHY requires a bring-up process to ensure normal operating. The PMA bring-up is user-triggered and requires configuring a few registers.

Registers 0x200 to 0x203 could be used to trigger a simple PMA bring-up process, and the steps are as follows.

1. Enable PRBS31 and internal serial loopback.
   1. Write 0x200 = 0x0D     (enable PRBS31 and internal serial loopback)
   2. Write 0x201 = 0x0
   3. Write 0x202 = 0x0
   4. Write 0x203 = 0x93     (this picks the opcode for SET_OPERATION_MODE)
   5. Read 0x207 until it becomes 0x80. This indicates that the operation was completed successfully.

2. Run initial adaptation. Enable mission mode, disable internal serial loopback and disable PRBS31.
   1. Write 0x200 = 0xE1     (medium adaptation effort for PAM4, disable PRBS after adaptation)
   2. Write 0x201 = 0x01     (disable internal serial loopback after adaptation)
   3. Write 0x202 = 0x01     (enable initial adaptation)
   4. Write 0x203 = 0x96     (this picks the opcode for START_ADAPTATION)
   5. Read 0x207 until it becomes 0x80. This indicates that the operation was completed successfully.

3. Check the link status with “rx_is_lockedtodata.”

Loading PMA Configuration Register SET_OPERATION_MODE

Loading PMA Configuration Register START_ADAPTATION

Some extra steps or different register values may be required depending on real transceiver design and link behavior.

• Static temperature flows (STF) and dynamic temperature flows (DTF) have different processes for successful link bring-up.

https://www.intel.com/content/www/us/en/programmable/documentation/kqh1479167866037.html#xld1535735424506

• If using a PMA configuration, load the PMA configuration is required

https://www.intel.com/content/www/us/en/programmable/documentation/kqh1479167866037.html#vrl1547592218047

• If RX simplex mode is used

https://www.intel.com/content/www/us/en/programmable/documentation/kqh1479167866037.html#xmz1573163945902

• If valid data rate traffic is not available at the RX, rerun initial adaptation until valid traffic is available

You can refer to the Intel E-Tile Transceiver PHY User Guide for further details.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_etile_xcvr_phy.pdf

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He Zhengmiao (James)